• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.481-487
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• 2013

To successfully accomplish a bit synchronization, a synchronizer should exploit a preamble pattern. A MFM (modified frequency modulation) flag is uses as a preamble in a PJM (phase jitter modulation) mode RFID standard. In the recent work, a synchronizer for a PJM mode tag was proposed, which is composed of several correlators. In this paper, we present a new bit synchronizer in which a coarse synchronization is done as in the previous work while a fine synchronization is performed via exploiting a violation bit included in the MFM flag. We show that the proposed synchronizer can significantly reduce the overall hardware complexity at the expense of slight burden to a demodulator structure. Through simulation, we also show that its performance is comparable to that of the previous system despite its hardware simplicity.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.6
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• pp.70-80
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• 2008

This paper presents comparison of 18000-3 ASK and PJM mode RFID in terms of reading speed. This is accomplished by counting the occurrences of a few representative blocks which constitute the reader / tag interactions for each mode. To apply FS (frame slotted)-aloha protocol, four Q-algorithms, which are a Q-algorithm suggested in the standard document, a fixed Q-algorithm, a minimum Q-algorithm and the number of tag dependent Q-algorithm, are used. Through some simulations, we present the reading speed of each mode with respect to the Q-algorithm and the comparison of the reading speed between the two modes for each Q-algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7C
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• pp.697-705
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• 2009

This paper presents the theoretical tag-reading speed in the ASK and the PJM mode of a 13.56MHz RFID system which have been adopted in the international standard ISO 18000-3, along with simulation results to support the mathematical analysis. Through the analysis using the number of tag-dependent Q-algorithm, which was known to give relatively fast reading speed, we not only derive the number of slots to read out given tags, but compare the reading speeds of the ASK with that of the PJM mode. Moreover, we present the numerical comparison of two modes which bring the equivalent results as in the theoretical one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1506-1513
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• 2009

This paper presents a synchronization method to determine the exact demodulation time using the MFM Flag of the 18000-3 PJM mode, along with the hardware structure to implement the proposed method. The proposed system detects an incipient peak using ITS(Initial Time Selector) and a correlator and achieves the final synchronization via identifying the peak position from the comparison of the outputs of two followed additional correlators. The peak detection algorithm and the choice of the templates of the correlators are described. Simulation results show that the proposed system performs successfully in noisy environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1B
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• pp.117-124
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• 2010

This paper presents a sampling based demodulation method of PJM signal and a hardware structure to implement the proposed demodulator. The proposed method, using matched filters in the discrete time domain, can make decisions on 4 different sampled signals caused by MFM encoding. We mathematically derive the BER of the proposed demodulation method and prove its validity through simulation results.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.2
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• pp.77-83
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• 2011

In this paper, we present the design procedure of the synchronizer and the demodulator of a 13.56MHz RFID PJM tag, which was standardized in ISO 18000-3 mode 3. We optimize the algorithms in order to minimize the number of registers and implement them based on international standard. The designed module is simulated by Modelsim and FPGA. The synchronizer is composed of 3 correlators that is implemented by 1,024(16bit ${\times}$ 64cycle) registers. The demodulator is composed of 2 correlators that is implemented by 128(2bit ${\times}$ 64cycle) registers. The simulation performed with the demodulator integrated with the synchronizer shows that it works at about 87% success rate with the test data of SNR -2dB and 100% with those of SNR 4dB.