• 제목/요약/키워드: PDN

검색결과 48건 처리시간 0.024초

GHz EMI Characteristics of 3D Stacked Chip PDN with Through Silicon Via (TSV) Connections

  • Pak, Jun-So;Cho, Jong-Hyun;Kim, Joo-Hee;Kim, Ki-Young;Kim, Hee-Gon;Lee, Jun-Ho;Lee, Hyung-Dong;Park, Kun-Woo;Kim, Joung-Ho
    • Journal of electromagnetic engineering and science
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    • 제11권4호
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    • pp.282-289
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    • 2011
  • GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

"Post-Decompressive Neuropathy": New-Onset Post-Laminectomy Lower Extremity Neuropathic Pain Different from the Preoperative Complaint

  • Boakye, Lorraine A.T.;Fourman, Mitchell S.;Spina, Nicholas T.;Laudermilch, Dann;Lee, Joon Y.
    • Asian Spine Journal
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    • 제12권6호
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    • pp.1043-1052
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    • 2018
  • Study Design: Level III retrospective cross-sectional study. Purpose: To define and characterize the presentation, symptom duration, and patient/surgical risk factors associated with 'post-decompressive neuropathy (PDN).' Overview of Literature: PDN is characterized by lower extremity radicular pain that is 'different' from pre-surgical radiculopathy or claudication pain. Although it is a common constellation of postoperative symptoms, PDN is incompletely characterized and poorly understood. We hypothesize that PDN is caused by an intraoperative neuropraxic event and may develop early (within 30 days following the procedure) or late (after 30 days following the procedure) within the postoperative period. Methods: Patients who consented to undergo lumbar laminectomy with or without an instrumented fusion for degenerative lumbar spine disease were followed up prospectively from July 2013 to December 2014. Relevant data were extracted from the charts of the eligible patients. Patient demographics and surgical factors were identified. Patients completed postoperative questionnaires 3 weeks, 3 months, 6 months, and 1 year postoperatively. Questions were designed to characterize the postoperative pain that differed from preoperative pain. A diagnosis of PDN was established if the patient exhibited the following characteristics: pain different from preoperative pain, leg pain worse than back pain, a non-dermatomal pain pattern, and nocturnal pain that often disrupted sleep. A Visual Analog Scale was used to monitor the pain, and patients documented the effectiveness of the prescribed pain management modalities. Patients for whom more than one follow-up survey was missed were excluded from analysis. Results: Of the 164 eligible patients, 118 (72.0%) completed at least one follow-up survey at each time interval. Of these eligible patients, 91 (77.1%) described symptoms consistent with PDN. Additionally, 75 patients (82.4%) described early-onset symptoms, whereas 16 reported symptoms consistent with late-onset PDN. Significantly more female patients reported PDN symptoms (87% vs. 69%, p=0.03). Patients with both early and late development of PDN described their leg pain as an intermittent, constant, burning, sharp/stabbing, or dull ache. Early PDN was categorized more commonly as a dull ache than late-onset PDN (60% vs. 31%, p=0.052); however, the difference did not reach statistical significance. Opioids were significantly more effective for patients with early-onset PDN than for those with late-onset PDN (85% vs. 44%, p=0.001). Gabapentin was most commonly prescribed to patients who cited no resolution of symptoms (70% vs. 31%, p=0.003). Time to symptom resolution ranged from within 1 month to 1 year. Patients' symptoms were considered unresolved if symptoms persisted for more than 1 year postoperatively. In total, 81% of the patients with early-onset PDN reported complete symptom resolution 1 year postoperatively compared with 63% of patients with late-onset PDN (p=0.11). Conclusions: PDN is a discrete postoperative pain phenomenon that occurred in 77% of the patients who underwent lumbar laminectomy with or without instrumented fusion. Attention must be paid to the constellation and natural history of symptoms unique to PDN to effectively manage a self-limiting postoperative issue.

De-Embedding 기술을 이용한 IC 내부의 전원분배망 추출에 관한 연구 (Novel Extraction Method for Unknown Chip PDN Using De-Embedding Technique)

  • 김종민;이인우;김성준;김소영;나완수
    • 한국전자파학회논문지
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    • 제24권6호
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    • pp.633-643
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    • 2013
  • IC 내부의 전원분배망(PDN: Power Delivery Network) 회로를 분석하기 위해서는 IC의 디자인 정보가 담긴 파일이 필요하지만, 상용 IC(Commercial IC)의 경우 보안상의 이유로 디자인 정보를 제공하지 않고 있다. 하지만 온-칩 전원분배망(On-chip PDN) 특성이 포함된 경우에는 PCB와 패키지의 특성만으로는 정확한 해석이 어려우므로 본 연구에서는 IC 내부의 정보가 제공하지 않는 전원분배망(PDN) 회로의 추출에 관하여 연구를 하였다. IC 내부의 전원분배망(PDN)의 주파수에 대한 특성을 추출하기 위하여, IEC62014-3에서 제안하고 있는 추출용 보드를 제작하였고, 추출용 보드를 구성하고 있는 SMA 커넥터, 패드, 전송 선로, 그리고 QFN 패키지의 주파수에 대한 특성들을 분석하였다. 추출된 결과들은 디임베딩(de-embedding) 기술에 적용하여 IC 내부의 전원분배망(PDN) 회로를 S-parameter 기반으로 모델을 추출하였고, 평가용 보드의 전원분배망 결합회로(PDN Co-simulation)모델에 적용하여 측정과 비교한 결과, ~4 GHz까지 잘 일치하였다.

유비쿼터스 컴퓨팅 환경에서 PDN의 구조와 결정 요인에 대한 정성적 연구 (A Qualitative Research on the Structure and Determinants of Personal Device Network in the Ubiquitous Computing Context)

  • 전석원;장윤선;김진우
    • Journal of Information Technology Applications and Management
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    • 제13권3호
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    • pp.1-28
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    • 2006
  • In the ubiquitous computing environments. people usually carry multiple information technology devices with them. Personal device network (PDN) refers to the way how people connect multiple IT devices for their personal as well as professional purposes. Even though it has been Quite popular to construct the PDN in ubiquitous computing context, not much research has been conducted on how people actually connected multiple devices and what influences their methods of connection. In this paper we conducted a content analysis on community bulletin boards of IT devices and a contextual inquiry with expert users of PDN for investigating the configurations with which users connect multiple IT devices. Base on the results of two related studies, we identified three major types of PDN configurations, and key factors that influence the configurations of PDN. We conclude this research with guidelines to design a set of devices for each of the three configuration types.

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파워 분배망을 고려한 디지털 회로 시스템의 설계와 분석 (Design and Analysis of Digital Circuit System Considering Power Distribution Networks)

  • 이상민;문규;위재경
    • 대한전자공학회논문지SD
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    • 제41권4호
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    • pp.15-22
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    • 2004
  • 이 논문은 PCB의 PDN(Power Distribution Network) 시스템을 고려한 채널 분석을 나타내었다. 설계자가 원하는 PDN 시스템을 설계하기 위하여, 전체 주파수 범위의 PDN이 요구하는 임피던스를 얻는 유용한 설계방법을 제안하였다. 제안된 방법은 주파수 영역과 관계된 계층적 배치 접관방식과 보트와 decoupling 커패시터 사이의 current 흐름의 간섭을 고려한 path-based equivalent 회로를 기본으로 하였다. 비록 빠르고 쉬운 계산을 위한 lumped model일지라도, 실험 결과는 제안된 모델이 numerical 분석처럼 거의 정확함을 보였다. PDN 시스텐의 분석은 패키지 인덕턴스가 파워 노이즈, 데이터 채널을 통한 신호 이동에 영향을 받는다는 것을 보여주고 있으나, 보드 PDN 또한 정확한 채널 신호를 위해 무시할 수 없다는 것을 보여준다. 따라서 설계자는 반드시 초고속 디지털 시스템의 첫 스팩 설계로부터 보드, 패키지, 칩 등을 동시에 디자인을 해야 한다.

비아 절단 구조를 사용한 DRAM 패키지 기판 (DRAM Package Substrate Using Via Cutting Structure)

  • 김문정
    • 대한전자공학회논문지SD
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    • 제48권7호
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    • pp.76-81
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    • 2011
  • 본 논문에서는 비아 절단 구조를 제안하고 2층 구조의 DRAM 패키지 기판 설계에 적용하여 낮은 임피던스를 가지는 파워 분배망(Power Distribution Network)을 구현하였다. 제안한 신규 비아 구조는 비아의 일부가 절단된 형태이고 본딩 패드와 결합하여 넓은 배선 면적을 필요로 하지 않는 장점을 가진다. 또한 비아 절단 구조를 적용한 설계에서는 본딩 패드에서 VSSQ까지의 배선 경로를 효과적으로 단축시킴으로써 PDN 임피던스를 개선시킬 수 있다. DRAM 패키지 기판 상의 윈도우 영역 형성과 동시에 비아의 일부 영역이 제거되므로 비아 절단 구조 제작을 위한 추가적인 공정은 없다. 또한 비아 홀 내부를 솔더 레지스트로 채움으로써 버(Burr) 발생을 최소화하였으며, 이를 패키지 기판 단면 촬영을 통해 검증하였다. 비아 절단 구조의 적용 및 VDDQ/VSSQ 배치에 의한 PDN 임피던스 변화를 검증하기 위해서 3차원 전자장 시뮬레이션 및 네트워크 분석기 측정을 통해 기존 방식을 적용한 패키지 기판과 비교 검증을 진행하였다. 신규 DRAM 패키지 기판은 대부분의 주파수 범위에서 보다 우수한 PDN 임피던스를 가졌으며, 이는 제안한 비아 절단 구조와 파워/그라운드 설계 배치가 PDN 임피던스 감소에 효과적임을 증명한다.

Analyzing the Impact of Supply Noise on Jitter in GBPS Serial Links on a Merged I/O-Core Power Delivery Network

  • Tan, Fern-Nee;Lee, Sheng Chyan
    • 마이크로전자및패키징학회지
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    • 제20권4호
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    • pp.69-74
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    • 2013
  • In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

원전 계측제어계통의 안전 네트워크 설계 및 평가를 위한 보안 기준 (Security Criteria for Design and Evaluation of Secure Plant Data Network on Nuclear Power Plants)

  • 김도연
    • 한국전자통신학회논문지
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    • 제9권2호
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    • pp.267-271
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    • 2014
  • 원자력발전소의 데이터 네트워크와 연관된 안전 계통들은 다양한 IT (information technology) 네트워크 및 응용프로그램들을 적용하여 현대화되고 있다. 발전소 데이터 네트워크의 출현과 더불어 원전 계측제어시스템들은 최신의 디지털화된 마이크로프로세서에 근간을 둔 시스템으로 진화하고 있는 반면에, 일반적인 IT 환경에서의 각종 정보시스템이 가지는 사이버보안 취약성 및 사고의 가능성이 증대되는 단점을 가지게 되었다. 이를 보완하기 위해 원전에 적용하는 데이터 네트워크는 신뢰성, 성능 및 보안요건을 충분히 고려해서 설계되어야 한다. 본 논문에서는 원전 계측제어계통에 적용되는 안전한 네트워크의 설계 및 평가 시 사용될 수 있는 기술적인 보안 기준들을 제시하였으며, 본 기준들을 적용하여 설계 및 운영되는 발전소 데이터 네트워크는 외부의 사이버 위협으로부터 효과적인 대처를 할 것으로 판단된다.

Power Distribution Network Modeling using Block-based Approach

  • Chew, Li Wern
    • 마이크로전자및패키징학회지
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    • 제20권4호
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    • pp.75-79
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    • 2013
  • A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

Efficient Decoupling Capacitor Optimization for Subsystem Module Package

  • Lim, HoJeong;Fuentes, Ruben
    • 마이크로전자및패키징학회지
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    • 제29권1호
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    • pp.1-6
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    • 2022
  • The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.