• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• Asian Spine Journal
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• v.12 no.6
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• pp.1043-1052
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• 2018

Study Design: Level III retrospective cross-sectional study. Purpose: To define and characterize the presentation, symptom duration, and patient/surgical risk factors associated with 'post-decompressive neuropathy (PDN).' Overview of Literature: PDN is characterized by lower extremity radicular pain that is 'different' from pre-surgical radiculopathy or claudication pain. Although it is a common constellation of postoperative symptoms, PDN is incompletely characterized and poorly understood. We hypothesize that PDN is caused by an intraoperative neuropraxic event and may develop early (within 30 days following the procedure) or late (after 30 days following the procedure) within the postoperative period. Methods: Patients who consented to undergo lumbar laminectomy with or without an instrumented fusion for degenerative lumbar spine disease were followed up prospectively from July 2013 to December 2014. Relevant data were extracted from the charts of the eligible patients. Patient demographics and surgical factors were identified. Patients completed postoperative questionnaires 3 weeks, 3 months, 6 months, and 1 year postoperatively. Questions were designed to characterize the postoperative pain that differed from preoperative pain. A diagnosis of PDN was established if the patient exhibited the following characteristics: pain different from preoperative pain, leg pain worse than back pain, a non-dermatomal pain pattern, and nocturnal pain that often disrupted sleep. A Visual Analog Scale was used to monitor the pain, and patients documented the effectiveness of the prescribed pain management modalities. Patients for whom more than one follow-up survey was missed were excluded from analysis. Results: Of the 164 eligible patients, 118 (72.0%) completed at least one follow-up survey at each time interval. Of these eligible patients, 91 (77.1%) described symptoms consistent with PDN. Additionally, 75 patients (82.4%) described early-onset symptoms, whereas 16 reported symptoms consistent with late-onset PDN. Significantly more female patients reported PDN symptoms (87% vs. 69%, p=0.03). Patients with both early and late development of PDN described their leg pain as an intermittent, constant, burning, sharp/stabbing, or dull ache. Early PDN was categorized more commonly as a dull ache than late-onset PDN (60% vs. 31%, p=0.052); however, the difference did not reach statistical significance. Opioids were significantly more effective for patients with early-onset PDN than for those with late-onset PDN (85% vs. 44%, p=0.001). Gabapentin was most commonly prescribed to patients who cited no resolution of symptoms (70% vs. 31%, p=0.003). Time to symptom resolution ranged from within 1 month to 1 year. Patients' symptoms were considered unresolved if symptoms persisted for more than 1 year postoperatively. In total, 81% of the patients with early-onset PDN reported complete symptom resolution 1 year postoperatively compared with 63% of patients with late-onset PDN (p=0.11). Conclusions: PDN is a discrete postoperative pain phenomenon that occurred in 77% of the patients who underwent lumbar laminectomy with or without instrumented fusion. Attention must be paid to the constellation and natural history of symptoms unique to PDN to effectively manage a self-limiting postoperative issue.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.633-643
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• 2013

GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

• Journal of Information Technology Applications and Management
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• v.13 no.3
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• pp.1-28
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• 2006

In the ubiquitous computing environments. people usually carry multiple information technology devices with them. Personal device network (PDN) refers to the way how people connect multiple IT devices for their personal as well as professional purposes. Even though it has been Quite popular to construct the PDN in ubiquitous computing context, not much research has been conducted on how people actually connected multiple devices and what influences their methods of connection. In this paper we conducted a content analysis on community bulletin boards of IT devices and a contextual inquiry with expert users of PDN for investigating the configurations with which users connect multiple IT devices. Base on the results of two related studies, we identified three major types of PDN configurations, and key factors that influence the configurations of PDN. We conclude this research with guidelines to design a set of devices for each of the three configuration types.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.15-22
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• 2004

This paper presents the channel analysis considering power distribution network(PDN) system of PCB. For achieve the target PDN system we proposed the useful design approach for acquiring the characteristic target of power distribution network in overall frequency ranges. The proposed method is based on the hierarchical approach related to frequency ranges and the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors and the board through it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. The analysis of PDN system shows that although the effective inductance of package dominatly affects the power noise and the signal transfer through data channel, the board PDNs also can not be neglected for achieving the accurate channel signaling. Therefore, we must design concurrently the chip, package, and board from the initial spec design of high speed digital system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.76-81
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• 2011

A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.2
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• pp.267-271
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• 2014

Nuclear power plant data networks and their associated safety systems are being modernized to include many information technology (IT) networks and applications. Along with the advancement of plant data networks (PDN), instrumentation and control systems are being upgraded with modern digital, microprocessor-based systems. However, nuclear PDN is confronted significant side-effects, which PDN is exposed to prevalent cyber threats typically found in IT environments. Therefore, cyber security vulnerabilities and possibilities of cyber incidents are dramatically increased in nuclear PDN. Consequently, it should be designed fully ensuring the PDN meet all reliability, performance and security requirements in order to overcome the disadvantages raised from adaption of IT technology. In this paper, we provide technical security criteria should be used in design and evaluation of secure PDN. It is believed PDN, which is designed and operated along with these technical security critera, effectively protect against possible outside cyber threats.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.1-6
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• 2022

The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.