• 제목/요약/키워드: PCB system

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Development of Frequency Weighing Sensor and Single Crystal Growth (새로운 무게센서 재발과 단결정성장(1))

  • Jang Y.N.;Sung N.H.;Chae S.C.;Bae I.K.;Kim I.J.
    • Korean Journal of Crystallography
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    • v.8 no.1
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    • pp.38-47
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    • 1997
  • A new weighing sensor for the automatic diameter control system of the crystal growth is developed in this study. This weighing sensor measures the frequency of the vibrating element which is lineally changing with respect to weight. The signal and the power of this system are transmitted without any physical contact, so that this sensor offers high accuracy and resolution. This system consists of a string, a sinusoidal wave generator, an automatic amplification adjusting circuit, signal transformers and a PCB. 4 kinds of programs are developed for checking DAC, weight calibration and controlling growth process. The measurements of the standard deviation and the resolution show $\pm0.10g$(measured at every second) and $5{\times}10^{-5}$, respectively, This weighing sensor is effective under high pres-sure of 200 atm, high temperature and vacuum condition. The weighing system can control the temperature in the accuracy of $\pm0.025^{\circ}C$ with the 'signal divider'. The optical quality single crystals of $(YGd)_3Sc_2Ga_3O_{12},\;Er-Y_3Sc_2Al_3O_{12},\;and\;Bi_{12}GeO_{20}$ have been grown by Czo-chralski method using this auto-diameter control system.

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A Study on the Chlorobenzene and Chlorophenol Behavior in Plasma Type Pyrolysis/Gasfication/Melting Process (플라즈마 방식 열분해 가스화용융시설의 공정별 클로로벤젠 및 클로로페놀 배출거동에 관한 연구)

  • Shin, Chan-Ki;Shin, Dae-Yun;Kim, Ki-Heon;Son, Ji-Whan
    • Journal of environmental and Sanitary engineering
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    • v.22 no.2
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    • pp.9-20
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    • 2007
  • The incineration process has commonly used for wastes amount reduction and thermal treatments of pollutants as the technologies accumulated. However, the process is getting negative public images owing to matter of hazardous pollutants emission. Specially dioxins became a main issue and were mostly emitted from municipal solid wastes incineration. In this reason, pyrolysis/gasification/melting process is presented as an alternative of incineration process. The pyrolysis/gasification/melting process, a novel technology, is middle of verification of commercial plant and development of technologies in Korea. But the survey about the pollutant emission from the process, and background data in these facilities is necessary. So in this survey, t is investigated that the behavior of chlorobenzenes and chlorophenols in plasma type pyrolysis/gasification/melting plant of pilot scale. We investigated discharging behavior of each phase of chlorobenzene through each process in the plsasma type pyrolysis/gasification/melting process. From this result, it was found that about 99 percent of particle-phase chlorobenzene was removed, but on the other hand gas-phase chlorobenzene was increased by about 600 percent through heat exchanger, flue gas cooling, system and semi dry absorption bag filter(SDA/BF). Also, this investigation presented that di-chlorobenzene(DCB) tri-chlorobenzene(TCB), tetra-chlorobenzene(TeCB), penta-chlorobenzene (PCB), except mono-chlorobenzene(MCB) and hexa-chlorobenzene(HCB) were increased through the flue gas cooling system and the semi dry absorption bag filter(SDA/BF). It was investigated that concentration of particle-phase chlorophenol was decreased by about 66 percent, but on the other hand, concentration of gas-phase chlorophenol was increased by about 170 percent through heat exchanger, flue gas cooling system, and semi dry absorption bag filter(SDA/BF). Also, it was found that di-chlorophenol(DCP), tri-chlorophenol(TCP), and penta-chlorophenol(PCP) were increased through the flue gas cooling system, and the semi dry absorption bag filter(SDA/BF). It can be considered that small-scale pilot facility and short investigation period might cause the concentration increase through the flue gas cooling system and the semi dry absorption bag filter(SDA/BF). A further study on real-scale pilot facility and accurate investigation may be required.

Radio Frequency Circuit Module BGA(Ball Grid Array) (Radio Frequency 회로 모듈 BGA(Ball Grid Array) 패키지)

  • Kim, Dong-Young;Jung, Tae-Ho;Choi, Soon-Shin;Jee, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.1
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    • pp.8-18
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    • 2000
  • We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

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Design and Implementation of Mobile Phone Interface Module for DGPS Correction Message Transmission (DGPS 보정신호 전송을 위한 휴대전화 인터페이스 모듈의 설계 및 구현)

  • Yi, Jae-hoon;Kim, Chang-Soo;Jeong, Seong-Hoon;Lee, Tae-Oh;Yun, Hee-Chul;Yim, Jae-Hong
    • Journal of Navigation and Port Research
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    • v.26 no.4
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    • pp.419-426
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    • 2002
  • The conventional RTK-GPS technique has many problems which are permission using RF wireless modem, influence of geographic obstacle using radio wave, frequency interference, finiteness of frequency resources. To solve these problems, in this paper, we designed the DGPS correction message transmission system as a method to substitute the RF wireless modem of RTK-DGPS receiver. Then the interface module was designed and implemented for linkage of GPS receiver and mobile phone. As a result worked differential surveying using receiving correction message using RS-232C and communication control, users of mobile station were worked differential surveying correction between mobile phones. Interface module system was received the same result of precision which was compared RF wireless modem system.

Development and Verification of Modular 3U Cubesat Standard Platform (3U 큐브위성 표준 플랫폼의 개발)

  • Song, Sua;Lee, Soo-Yeon;Kim, Hongrae;Chang, Young-Keun
    • Journal of Aerospace System Engineering
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    • v.11 no.5
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    • pp.65-75
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    • 2017
  • This study proposes development of 3U CubeSat standard platform whose function and performance are verified via KAUSAT-5 development. 3U CubeSat platform specification was selected for the design of 3U Cubesat standard platform by examining existing CubeSat and state-of-art technology, and consequently a universally usable 3U CubeSat platform was designed. Standard platform was manufactured in 1.5U size and developed with a modular concept to be able to add and expand payloads and ADCS actuators for meeting the user's needs. In addition, in case of the power system, the solar panel, the battery, and the deployment mechanism are designed to be configured by the user. In the mechanical system design of a standard platform, subsystem and micro equipment functions/performance could be integrated and miniaturized on micro-sized PCBs and maximized electrical capability to accommodate multiple payloads. In the development of the 3U CubeSat, the satellite platform adopts the developed standard platform, which can reduce the cost and schedule for the whole satellite development by reducing the additional function verification.

Low Power 4-Gb/s Receiver for GND-referenced Differential Signaling (접지기반 차동신호 전송을 위한 저전력 4-Gb/s 수신단 설계)

  • Lee, Mira;Kim, Seok;Jeong, Youngkyun;Bae, Jun-Han;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.244-250
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    • 2012
  • This paper describes a 4-Gb/s receiver circuit for a low-swing ground-referenced differential signaling system. The receiver employs a common-gate level-shifter and a continuous linear equalizer which compensates inter-symbol-interference (ISI) and improves voltage and timing margins. A bias circuit maintains the bias current of the level-shifter when the common level of the input signal changes. The receiver is implemented with a low-power 65-nm CMOS technology. When 4-Gb/s 400mVp-p signals are transmitted to the receiver through the channel with the attenuation of -19.7dB, the timing margin based on bit error rate (BER) of $10^{-11}$ is 0.48UI and the power consumption is as low as 0.30mW/Gb/s.

Filed Programmable Logic Control and Test Pattern Generation for IoT Multiple Object switch Control (사물인터넷 환경에서 다중 객체 스위치 제어를 위한 프로그래밍 가능한 로직제어 및 테스트 패턴 형성)

  • Kim, Eung-Ju;Jung, Ji-Hak
    • Journal of Internet of Things and Convergence
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    • v.6 no.1
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    • pp.97-102
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    • 2020
  • Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

Preparation of Soft Etchant to Improve Adhesion Strength between Photoresist and Copper Layer in Copper Clad Laminates (CCL 표면과 포토리지스트와의 접착력 향상 위한 Soft 에칭액의 제조)

  • Lee, Soo;Moon, Sung-Jin
    • Journal of the Korean Applied Science and Technology
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    • v.32 no.3
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    • pp.512-521
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    • 2015
  • In this research, environmental friendly organic acid containing microetching system to improve adhesion strength between photoresist resin and Copper Clad Laminate(CCL) was developed without using strong oxidant $H_2O_2$. Etching rate and surface contamination on CCL were examined with various etching conditions with different etchants, organic acids and additives. to develope an optimum microetching condition. Etching solution with 0.04 M acetic acid showed the highest etching rate $0.4{\mu}m/min$. Etching solution with the higher concentration of APS showed the higher etching rate but surface contamination on CCL is very serious. In addition, stabilizer solution also played an important role to control the surface contamination. As a result of research, the etching solution containing 0.04 M of acetic acid, 0.1 M of APS with 4 g/L of stabilizer solution(ST-1) was best to improve adhesion between CCL and photoresist resin as well as showed the most clean and rough surface with the etching rate of $0.37{\mu}m/min$.

Empirical Model of Via-Hole Structures in High-Count Multi-Layered Printed Circuit Board (HCML 배선기판에서 비아홀 구조에 대한 경험적 모델)

  • Kim, Young-Woo;Lim, Yeong-Seog
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.12
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    • pp.55-67
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    • 2010
  • The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.

Flip Chip Assembly Using Anisotropic Conductive Adhesives with Enhanced Thermal Conductivity

  • Yim, Myung-Jin;Kim, Hyoung-Joon;Paik, Kyung-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.1 s.34
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    • pp.9-16
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    • 2005
  • This paper presents the development of new anisotropic conductive adhesives with enhanced thermal conductivity for the wide use of adhesive flip chip technology with improved reliability under high current density condition. The continuing downscaling of structural profiles and increase in inter-connection density in flip chip packaging using ACAs has given rise to reliability problem under high current density. In detail, as the bump size is reduced, the current density through bump is also increased. This increased current density also causes new failure mechanism such as interface degradation due to inter-metallic compound formation and adhesive swelling due to high current stressing, especially in high current density interconnection, in which high junction temperature enhances such failure mechanism. Therefore, it is necessary for the ACA to become thermal transfer medium to improve the lifetime of ACA flip chip joint under high current stressing condition. We developed thermally conductive ACA of 0.63 W/m$\cdot$K thermal conductivity using the formulation incorporating $5 {\mu}m$ Ni and $0.2{\mu}m$ SiC-filled epoxy-bated binder system to achieve acceptable viscosity, curing property, and other thermo-mechanical properties such as low CTE and high modulus. The current carrying capability of ACA flip chip joints was improved up to 6.7 A by use of thermally conductive ACA compared to conventional ACA. Electrical reliability of thermally conductive ACA flip chip joint under current stressing condition was also improved showing stable electrical conductivity of flip chip joints. The high current carrying capability and improved electrical reliability of thermally conductive ACA flip chip joint under current stressing test is mainly due to the effective heat dissipation by thermally conductive adhesive around Au stud bumps/ACA/PCB pads structure.

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