• 전기의세계
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• 제30권10호
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.162-165
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• 2000

To investigate the effect of metal electrode in electroluminescent[EL] devices, we fabricated EL devices of ITO/P3HT/Al, ITO/P3HT/LiF/Al and ITO/P3HT/Mg:In structure. In current-voltage-light power characteristics, turn-on voltage of EL devices using LiF insulating layer and Mg:In(2.8V) metal electrode is lower than EL device using Al(4.2V). Besides the external quantum efficiency is improved also. The reason is related to carrier mobility and carrier injection, which would affect the hole-electron balance. In the device with Al electrode, holes injected from indium-tin-oxide[ITO] to poly(3-hexylthiophene)[P3HT] might reach the Al electrode without interacting with injected electrons, because the electron injection efficiency was very low for this electrode. Besides oxidation of the Al electrode is likely due to holes reaching the cathode without meeting injected electrons. Another possible reason for the higher EL efficiency may be the insulating layer playing the role of a tunneling barrier for holes to the Al electrode. In all EL devices, the orange-red light was clearly visible in a dark room. Maximum peak wavelength of EL spectrum emitted at 640nm in accordance with photon energy 1.9eV

• 센서학회지
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• 제6권5호
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• pp.407-413
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• 1997

기판온도 $300^{\circ}C$에서 열증착법에 의해 p형 <100> Si 기판위에 CuPc(Copper Phthalocyanine) 결정 박막을 증착하였다. X선 회절분석으로부터 CuPc 박막은 a-축 방향으로 성장하였음을 알 수 있었다. CuPc분자들이 기판면위에 수직인 CuPc/Si박막의 광전특성을 조사하기 위하여 수직방향의 전류-전압 (I-V) 특성을 기판 Si의 특성과 비교 관찰하였다. 저항성 접촉을 위해 기판인 p형 Si위에 전극으로 Au를 증착시켰다. Au/Si 접합에 빛을 조사한 결과 전류는 증가하지만 광기전력효과는 관찰되지 않았다. p형 반도체인 CuPc 박막과 기판 p-Si의 접합은 장벽을 형성하지 않기 때문에 빛을 조사하지 않았을 때의 I-V 특성은 저항성을 나타낸다. 빛을 조사하였을 때 CuPc/Si 접합의 증가된 광전류는 Si 웨이퍼보다 현저하게 큰 것을 알 수 있다. 따라서 CuPc 층이 600 nm 파장에서의 붉은 빛을 현저하게 흡수하여 광전류에 기여하는 다량의 광캐리어를 형성함을 알 수 있다. CuPc/Si 박막은 $J_{sc}$ (short-circuit photocurrent) $4.29\;mA/cm^{2}$와 $V_{oc}$ (open circuit photovoltage) 12 mV의 광기전력 특성을 보여준다.

• 한국재료학회지
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• 제23권3호
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• pp.161-167
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• 2013

The ZnO thin films were grown on GaN template substrates by RF magnetron sputtering at different RF powers and n-ZnO/p-GaN heterojunction LEDs were fabricated to investigate the effect of the RF power on the characteristics of the n-ZnO/p-GaN LEDs. For the growth of the ZnO thin films, the substrate temperature was kept constant at $200^{\circ}C$ and the RF power was varied within the range of 200 to 500W at different growth times to deposit films of 100 nm thick. The electrical, optical and structural properties of ZnO thin films were investigated by ellipsometry, X-ray diffraction (XRD), atomic force microscopy (AFM), photoluminescence (PL) and by assessing the Hall effect. The characteristics of the n-ZnO/p-GaN LEDs were evaluated by current-voltage (I-V) and electroluminescence (EL) measurements. ZnO thin films were grown with a preferred c-axis orientation along the (0002) plane. The XRD peaks shifted to low angles and the surface roughness became non-uniform with an increase in the RF power. Also, the PL emission peak was red-shifted. The carrier density and the mobility decreased with the RF power. For the n-ZnO/p-GaN LED, the forward current at 20 V decreased and the threshold voltage increased with the RF power. The EL emission peak was observed at approximately 435 nm and the luminescence intensity decreased. Consequently, the crystallinity of the ZnO thin films grown with RF sputtering powers were improved. However, excess Zn affected the structural, electrical and optical properties of the ZnO thin films when the optimal RF power was exceeded. This excess RF power will degrade the characteristics of light emitting devices.

• 폴리머
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• 제25권3호
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• pp.399-405
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• 2001

Poly[3-octylthiophene-co-3-(4-fluorophenyl)thiophene]를 2:1, 1:1, 1:2의 몰 비로 공중합한 뒤 유기 발광 소자를 제작하였다. 이렇게 공중합한 고분자의 광ㆍ전기적인 특성을 PL, EL 스펙트럼과 I-V, V-L 곡선을 이용하여 조사하였고, 전자 흡수 스펙트럼과 순환 전압 전류 곡선을 이용하여 band diagram을 얻었다. P(OT/FPT)(1:1)의 경우 LUMO 값이 -3.35eV로 가장 낮았다. EL과 PL 스펙트럼에서는 fluorophenyl 기의 함량이 증가함에 따라 발광 파장이 장파장으로 이동하였으나, P(OT/FPT)(1:2)의 경우에는 단파장으로 이동하였다 이것은 fluoro-phenyl 기의 함량이 증가하여 고분자 사슬이 뒤틀리게 되어 ${\pi}$-conjugation이 깨어져 공액 길이가 짧아지는 효과를 나타냈기 때문이다. P(OT/FPT)(1:1)는 34cd/$m^2$으로 가장 우수한 휘도를 갖는 짙은 적색 발광을 하였다. 또한 발광 효율에서도 P(OT/FPT)(1:1)가 가장 우수한 것으로 나타났다. P(OT/FPT)(1:2)의 경우 필름 표면이 고르지 못하여 국부적으로 누설 전류가 흐르기 때문에 발광 효율이 낮아지는 것으로 믿어진다.

• 터널과지하공간
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• 제21권6호
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• pp.460-470
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• 2011

자연환경하에 있는 암석의 풍화특성과 풍화된 암석의 강도평가를 위하여 다양한 크기의 아소 가족묘비석을 대상으로 탄성파 속도를 측정하였다. 그 결과 크기가 다른 시료를 동일한 크기로 환산하여 탄성파 속도를 평가하는 크기 보정법과 새로운 암석 풍화지표로서 NET(Normalized Elapsed Time)를 제안하였다. 또한 NET을 이용한 암석 풍화 분류로부터 풍화암석에 대한 강도를 추정하였다. 용결응회암의 경우 탄성파 속도는 높고 속도저하는 거의 나타나지 않았지만, 안산암의 경우 탄성파 속도는 낮고 속도저하 현상이 관찰되었다. $V_p/V_o$-NET 곡선에 근거한 NET를 이용할 경우 크기가 다른 다양한 암석에 대해 같은 크기로 풍화정도를 비교할 수 있을 것으로 판단된다. 또한 $S_c/S_o$-NET 곡선에 의한 NET을 이용하여 암석의 풍화단계 분류가 가능하였으며, 이것으로부터 풍화 암석에 대한 강도추정도 가능하였다.

• 한국전기전자재료학회논문지
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• 제14권7호
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• pp.546-550
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• 2001

A new Lateral Trench Insulated Gate Bipolar Transistor(LTIGBT) with p$^{+}$ diverter was proposed to improve the characteristics of the conventional LTIGBT. The forward blocking voltage of the proposed LTIGBT with p$^{+}$ diverter was about 140V. That of the conventional LTIGBT of the same size was 105V. Because the p$^{+}$ diverter region of the proposed device was enclosed trench oxide layer, he electric field moved toward trench-oxide layer, and punch through breakdown of LTIGBT with p$^{+}$ diverter was occurred, lately. Therefore, the p$^{+}$ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. The Latch-up current densities of the conventional LTIGBT and proposed LTIGBT were 540A/$\textrm{cm}^2$, and 1453A/$\textrm{cm}^2$, respectively. The enhanced latch-up capability of the proposed LTIGBT was obtained through holes in the current directly reaching the cathode via the p$^{+}$ divert region and p$^{+}$ cathode layer beneath n$^{+}$ cathode layer./ cathode layer.

• 한국광학회:학술대회논문집
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• 한국광학회 1989년도 제4회 파동 및 레이저 학술발표회 4th Conference on Waves and lasers 논문집 - 한국광학회
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• pp.196-200
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• 1989

The physical properties related to the GaInAs/InP crystal grown by LPE are discussed in terms of both the design and operation characteristics of the GaInAs/InP Pin photodiode has cutoff frequency of 358 MHz and responsivity, 0.53 A/W (λ=1.3${\mu}{\textrm}{m}$), with dark current density as low as 4$\times$10-4/$\textrm{cm}^2$ under reverse bias voltage of 5V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1270-1273
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• 1997

We have investigated the latchup characteristics of BL/BILLI retrograde twin well CMOS that has the high energy ion implanted buried layer to intend for more improvement of latchup compare to conventional retrograde well and BILLI structures. We explored the dependence of various latchup characteristics such as n+ trigger latchup and p+ trigger latchup on the buried layer implant doses. We show various DC latchup characteristics that allow us to evaluate each technology and suggest guidelines for the reduction of latchup susceptibility.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.60-61
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• 2007

In this paper, the p-channel poly Si thin-film transistors (Poly-Si TFT's) using formed by solid phase crystallization (SPC) on glass substrate were fabricated. And we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's to indicate non-volatile memory (NVM) effect. Poly-Si TFT is investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, on/off current ratio. NVM characteristics is showed by measuring the threshold voltage change of TFT through I-V characteristics.