• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.122.1-122.1
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• 2011

Phosphorus is known to pile-up at the silicon surface when it is thermally oxidized. A thin layer, about 40nm thick from the silicon surface, is created containing more phosphorus than the bulk of the emitter. This layer has a gaussian profile with the peak at the surface of the silicon. In this study the pile-up effect was studied if this layer can act as a front surface field for solar cells. The effect was also tested if its high dose of phosphorus at the silicon surface can lower the contact resistance with the front metal contact. P-type wafers were first doped with phosphorus to create an n-type emitter. The doping was done using either a furnace or ion implantation. The wafers were then oxidized using dry thermal oxidation. The effect of the pile-up as a front surface field was checked by measuring the minority carrier lifetime using a QSSPC. The contact resistance of the wafers were also measured to see if the pile-up effect can lower the series resistance.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.243-247
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• 2012

The paper focuses on an anti-reflection (AR) coating deposited by PECVD in silicon solar cell fabrication. AR coating is effective to reduce the reflection of the light on the silicon wafer surface and then increase substantially the solar cell conversion efficiency. In this work, we carried out experiments to optimize double AR coating layer with silicon nitride and silicon oxide for the silicon solar cells. The p-type mono crystalline silicon wafers with $156{\times}156mm^2$ area, 0.5-3 ${\Omega}{\cdot}cm$ resistivity, and $200{\mu}m$ thickness were used. All wafers were textured in KOH solution, doped with $POCl_3$ and removed PSG before ARC process. The optimized thickness of each ARC layer was calculated by theoretical equation. For the double layer of AR coating, silicon nitride layer was deposited first using $SiH_4$ and $NH_3$, and then silicon oxide using $SiH_4$ and $N_2O$. As a result, reflectance of $SiO_2/SiN_x$ layer was lower than single $SiN_x$ and then it resulted in increase of short-circuit current and conversion efficiency. It indicates that the double AR coating layer is necessary to obtain the high efficiency solar cell with PECVD already used in commercial line.

• Journal of Information Display
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• v.8 no.1
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• pp.1-5
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• 2007

We have developed a CMOS LTPS process which requires only five photolithographic masks and only one ion doping step. Drain/Source areas of NMOS TFTs were formed by PECVD deposition of a highly doped precursor layer while PMOS contact areas were defined by ion implantation. Single TFTs, inverters, ring oscillators and shift registers were fabricated. N and p-channel devices reached field effect mobilities of $173cm^2$/Vs and $47cm^2$/Vs, respectively.

• Current Photovoltaic Research
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• v.4 no.1
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• pp.12-15
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• 2016

Screen printing technique followed by firing has commonly been used as metallization for both laboratory and industrial based solar cells. In the solar cell industry, the firing process is usually conducted in a belt furnace and needs to be optimized for fabricating high efficiency solar cells. The printed-Al layer on the silicon is rapidly heated at over $800^{\circ}C$ which forms a layer of back surface field (BSF) between Si-Al interfaces. The BSF layer forms $p-p^+$ structure on the rear side of cells and lower rear surface recombination velocity (SRV). To have low SRV, deep $p^+$ layer and uniform junction formation are required. In this experiment, firing process was carried out by using conventional tube furnace with $N_2$ gas atmosphere to optimize $V_{oc}$ of laboratory cells. To measure the thickness of BSF layer, selective etching was conducted by using a solution composed of hydrogen fluoride, nitric acid and acetic acid. The $V_{oc}$ and pseudo efficiency were measured by Suns-$V_{oc}$ to compare cell properties with varied firing condition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.144-145
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• 2006

ZnO is a promising material to make high efficiency violet or blue light emitting diodes (LEDs) for its large binding energy (60meV) and big bandgap. But the high quality p-type conduction of ZnO is a dilemma to achieve LEDs with it. In present study, we presented a reliable method to prepare ZnO thin films on (100)silicon substrates by RF magnetron sputtering in the mixture ambient of $N_2$ and $O_2$, accompanying with low pressure annealing in the sputtering chamber in $O_2$ at $600^{\circ}C$ and $800^{\circ}C$ respectively. X-ray diffraction and Hail effect with Van der Paul method were performed to test ZnO films. Seeback effect was also carried out to identify carrier types in ZnO films and showed the N-doped ZnO film annealed at $800^{\circ}C$ had achieved p-type conduction.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.23-27
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• 2011

Fabrication of porous silicon(PS) double layer by electrochemical etching is the first step in process of ultrathin solar cell using PS layer transfer process. The porosity of the porous silicon layer can be controlled by regulating the formation parameters such as current density and HF concentration. PS layer is fabricated by electrochemical etching in a chemical mixture of HF and ethanol. For electrochemical etching, highly boron doped (100) oriented monocrystalline Si substrates was used. Ths resistivity of silicon is $0.01-0.02\;{\Omega}{\cdot}cm$. The solution composition for electrochemical etching was HF (40%) : $C_2H_5OH$(99 %) : $H_2O$ = 1 : 1 : 2 (by volume). In order to fabricate porous silicon double layer, current density was switched. By switching current density from low to high level, a high-porosity layer was fabricated beneath a low-porosity layer. Etching time affects only the depth of porous silicon layer.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.27.1-27.1
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• 2009

In recent years, ZnO nanostructures have drawn considerable attentions for the development of futuristic electronic devices due to their superior structural and optical properties. As the growth of ZnO nanowires by MOCVD is a bottom-up technique, the nature of substrates has a vital role for the dimension and alignment of the nanowires. However, in the pursuit of next generation ZnO based nanodevices, it would be highly preferred if well-ordered ZnO nanowires could be obtained on various substrates like sapphire, silicon, glass etc. Vertically aligned nanowires were grown on A and C-plane sapphire substrates, where as nanopencils were obtained on R-plane sapphire substrates. In addition, C-axis oriented vertical nanowires were also found using an interfacial layer(aluminum nitride film) on silicon substrates. On the other hand, long nanowires were found on Ga-doped ZnO film on glass substrates. Structural and optical properties of the ZnO nanowires on various substrates were also investigated.

• Advances in nano research
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• v.2 no.1
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• pp.23-56
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• 2014

The significant growth of the Si photovoltaic industry has been so far limited due to the high cost of the Si photovoltaic system. In this regard, the most expensive factors are the intrinsic cost of silicon material and the Si solar cell fabrication processes. Conventional Si solar cells have p-n junctions inside for an efficient extraction of light-generated charge carriers. However, the p-n junction is normally formed through very expensive processes requiring very high temperature (${\sim}1000^{\circ}C$). Therefore, several systems are currently under study to form heterojunctions at low temperatures. Among them, carbon nanotube (CNT)/Si hybrid solar cells are very promising, with power conversion efficiency up to 15%. In these cells, the p-type Si layer is replaced by a semitransparent CNT film deposited at room temperature on the n-doped Si wafer, thus giving rise to an overall reduction of the total Si thickness and to the fabrication of a device with cheaper methods at low temperatures. In particular, the CNT film coating the Si wafer acts as a conductive electrode for charge carrier collection and establishes a built-in voltage for separating photocarriers. Moreover, due to the CNT film optical semitransparency, most of the incoming light is absorbed in Si; thus the efficiency of the CNT/Si device is in principle comparable to that of a conventional Si one. In this paper an overview of several factors at the basis of this device operation and of the suggested improvements to its architecture is given. In addition, still open physical/technological issues are also addressed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.758-765
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• 1986

The design, fabrication and performance of vertical double diffused power MOSFET (VDMOS) were described. On the antimony (Sb) doped (~7x10**17 cm**-3) silicon substrate (N+), epitaxial layer(N-) was grown. The thickness and the resistivity of this layer were 32\ulcorner and about 12\ulcorner-cm, respectively. The P- channel length which was controlled by sequential P-/N+ double diffuison method was about 1~2 \ulcorner, and was processed with the self alignment of 21 \ulcorner width poly silicon. To improve the breakdown voltage with constant on-resistance (Ron) about 1\ulcorner, three P+ guard rings were laid out around main pattern. With chip size of 4800\ulcorner x4840 \ulcorner, the VDMOS has shown breakdown voltage of 410~440V, on-resistance within 1.0~1.2\ulcornerand the current capablity of more than 5A.

• 한국태양에너지학회:학술대회논문집
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• 2011.11a
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• pp.245-248
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• 2011

Many researches have been carried out to improve light absorption in the crystalline silicon solar cell fabrication. The rear reflection is applied to increase the path length of light, resulting in the light absorption enhancement and thus the efficiency improvement mainly due to increase in short circuit current. In this paper, we manufactured the silicon solar cell using the mono crystalline silicon wafers with $156{\times}156mm^2$, 0.5~3.0 ${\Omega}{\cdot}cm$ of resistivity and p-type. After saw damage removal, the dielectric film ($SiN_x$)on the back surface was deposited, followed by surface texturing in the KOH solution. It resulted in single-side texturing wafer. Then the dielectric film was removed in the HF solution. The silicon wafers were doped with phosphorus by $POCl_3$ with the sheet resistance 50 ${\Omega}/{\Box}$ and then the silicon nitride was deposited on the front surface by the PECVD with 80nm thickness. The electrodes were formed by screen-printing with Ag and Al paste for front and back surface, respectively. The reflectance and transmittance for the single-sided and double-sided textured wafers were compared. The double-sided textured wafer showed higher reflectance and lower transmittance at the long wavelength region, compared to single-sided. The completed crystalline silicon solar cells with different back surface texture showed the conversion efficiency of 17.4% for the single sided and 17.3% for the double sided. The efficiency improvement with single-sided textured solar cell resulted from reflectance increase on back surface and light absorption enhancement.