• 대한전자공학회논문지SD
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• 제49권1호
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• pp.1-7
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• 2012

산화물 박막트랜지스터를 이용하여 액정 디스플레이 패널에 내장할 수 있는 새로운 게이트 드라이버 회로를 설계하고 제작하였다. 산화물 박막트랜지스터는 문턱전압이 음의 값을 갖는 경우가 많기 때문에 본 회로에서는 음의 게이트 전압을 인가하여 트랜지스터를 끄는 방법을 적용하였다. 또한 세 개의 풀다운 트랜지스터를 병렬로 배치하고 번갈아 사용하므로 안정적인 동작이 가능하다. 제안한 회로는 트랜지스터의 문턱전압이 -3 V ~ +6 V인 범위에서 정상적으로 동작하는 것을 시뮬레이션을 통해서 확인하였으며, 실제로 유리 기판 상에 제작하여 안정적으로 동작하는 것을 검증하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.205-205
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• 2015

최근, 비정질 산화물 반도체를 이용한 TFT는 투명성, 유연성, 저비용, 저온공정이 가능하기 때문에 차세대 flat-panel 디스플레이의 back-plane TFT로써 다양한 방면에서 연구되고 있다. 산화물 반도체 In-Zn-O-시스템에서는 Gallium (Ga)을 suppressor로 사용한 a-In-Ga-Zn-O (a-IGZO) 뿐만 아니라, Magnesium (Mg), Hafnium (Hf), Tin (Sn), Zirconium (Zr) 등의 다양한 물질이 연구되었다. 그 중 Silicon (Si)은 Ga, Hf, Sn, Zr, Mg과 같은 suppressor에 비해 구하기 쉬우며 가격적인 측면에서도 저렴하다는 장점이 있다. solution 공정으로 제작한 산화물 반도체 TFT는 진공 시스템을 사용한 공정보다 공정시간이 짧고, 저비용, 대면적화가 가능하다는 장점이 있다. 하지만, 투명하고 유연한 device를 제작하기 위해서는 저온 공정과 low thermal budget은 필수적이다. 이러한 측면에서 MWI (Microwave Irradiation)는 저온공정이 가능하며, 짧은 공정 시간에도 불구하고 IZO 시스템의 산화물 반도체의 전기적 특성 향상을 기대할 수 있는 효율 적인 열처리 방법이다. 본 연구에서는 In-Zn-O 시스템의 TFT에서 silicon (Si)를 Suppressor로 사용한 a-Si-In-Zn-O (SIZO) TFT를 제작하여 두 가지 열처리 방법을 사용하여 TFT의 전기적 특성을 확인하였다. 첫 번째 방법은 Box Furnace를 사용하여 N2 분위기에서 $600^{\circ}C$의 온도로 30분간 열처리 하였으며, 두 번째는 MWI를 사용하여 1800 W 출력 (약 $100^{\circ}C$)에 2분간 열처리 하였다. MWI 열처리는 Box Furnace 열처리에 비해 저온 공정 및 짧은 시간에도 불구하고 향상된 전기적 특성을 확인 할 수 있었다.

• 한국전기전자재료학회논문지
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• 제11권9호
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.91-92
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• 2007

이 논문에서는 다양한 채널길이에 따른 n-채널 다결정 실리콘 TFT의 특징을 보고한다. Excimer laser annealing (ELA)를 이용한 다결정 실리콘은 디스플레이의 재료로써 줄은 특성을 갖는다. 유리기판 위에 buffered oxide 층을 올리고 ELA 처리를 하여 다결정 실리콘을 제작 하였다. 그 위에 $SiO_2$, $SiN_x$를 증착시켜 n-채널 다결정 실리콘 TFT를 만들었다. 다양한 채널의 길이에 따른 n-채널 TFT의 문턱전압 ($V_{TH}$), ON/OFF 전류비($I_{ON}/I_{OFF}$), 포화 전륙(IDSAT)를 조사하였다. 그 결과 채널의 길이가 짧은 소자에서 더 줄은 TFT의 특징이 나타난다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.543-543
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• 2013

Thin-film transistors (TFTs) based on oxide semiconductors have been regarded as promising alternatives for conventional amorphous and polycrystalline silicon TFTs. Oxide TFTs have several advantages, such as low temperature processing, transparency and high field-effect mobility. Lots of oxide semiconductors for example ZnO, SnO2, In2O3, InZnO, ZnSnO, and InGaZnO etc. have been researched. Particularly, zinc-tin oxide (ZTO) is suitable for channel layer of oxide TFTs having a high mobility that Sn in ZTO can improve the carrier transport by overlapping orbital. However, some issues related to the ZTO TFT electrical performance still remain to be resolved, such as obtaining good electrical contact between source/drain (S/D) electrodes and active channel layer. In this study, the bottom-gate type ZTO TFTs with staggered structure were prepared. Thin films of ZTO (40 nm thick) were deposited by DC magnetron sputtering and performed at room temperature in an Ar atmosphere with an oxygen partial pressure of 10%. After annealing the thin films of ZTO at $400^{\circ}C$ or an hour, Cu, Mo, ITO and Ti electrodes were used for the S/D electrodes. Cu, Mo, ITO and Ti (200 nm thick) were also deposited by DC magnetron sputtering at room temperature. The channel layer and S/D electrodes were defined using a lift-off process which resulted in a fixed width W of 100 ${\mu}m$ and channel length L varied from 10 to 50 ${\mu}m$. The TFT source/drain series resistance, the intrinsic mobility (${\mu}i$), and intrinsic threshold voltage (Vi) were extracted by transmission line method (TLM) using a series of TFTs with different channel lengths. And the performances of ZTO TFTs were measured by using HP 4145B semiconductor analyzer. The results showed that the Cu S/D electrodes had a high intrinsic field effect mobility and a low effective contact resistance compared to other electrodes such as Mo, ITO and Ti.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.211.2-211.2
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• 2015

In order to investigate the effect of front channel in DAL (dual active layer) TFT (thin film transistor), we successfully fabricated DAL TFT composed of ITZO and IGZO as active layer using the solution process. In this structure, ITZO and IGZO active layer were used as front and back channel, respectively. The front channel was changed from 0.05 to 0.2 M at fixed 0.3 M IGZO of back channel. When the mol concentration of front channel was increased, the threshold voltage (VTH) was increased from 2.0 to -11.9 V and off current also was increased from 10-12 to 10-11. This phenomenon is due to increasing the carrier concentration by increasing the volume of the front channel. The saturation mobility of DAL TFT with 0.05, 0.1, and 0.2 M ITZO were 0.45, 4.3, and $0.65cm2/V{\cdot}s$. Even though 0.2 M ITZO has higher carrier concentration than 0.05 and 0.1 M ITZO, the 0.1 M ITZO/0.3 M IGZO DAL TFT has the highest saturation mobility. This is due to channel defect such as pores and pin-holes. These defect sites were created during deposition process by solvent evaporation. Due to these defect sites, the 0.1 M ITZO/0.3 M IGZO DAL TFT shows the higher saturation mobility than that of DAL TFT with front channel of 0.2 M ITZO.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.1-4
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• 2008

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method were evaluated, The polycrystalline silicon thin-film transistor (poly-Si TFT) has higher electric field-effect-mobility and larger drivability than the amorphous silicon TFT. However, to poly-Si TFT's using conventional processes, the temperature must be very high. For this reason, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248 nm)to fabricate a poly-Si film at low temperature. Then, High permittivity $HfO_2$ of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the Poly-Si TFT fabricated by the ELA crystallization method.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.301.2-301.2
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• 2016

Metal-oxide thin-film transistors (TFTs) have gained a considerable interest in transparent electronics owing to their high optical transparency and outstanding electrical performance even in an amorphous state. Also, these metal-oxide materials can be solution-processed at a low temperature by using deep ultraviolet (DUV) induced photochemical activation allowing facile integration on flexible substrates [1]. In addition, high-dielectric constant (k) inorganic gate dielectrics are also of a great interest as a key element to lower the operating voltage and as well as the formation of coherent interface with the oxide semiconductors, which may lead to a considerable improvement in the TFT performance. In this study, we investigated the electrical properties of solution-processed high-k strontium-doped AlOx (Sr-AlOx) gate dielectrics. Using the Sr-AlOx as a gate dielectric, indium-gallium-zinc oxide (IGZO) TFTs were fabricated and their electrical properties are analyzed. We demonstrate IGZO TFTs with a 10-nm-thick Sr-AlOx gate dielectric which can be operated at a low voltage (~5 V).

• 인포메이션 디스플레이
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• 제19권3호
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• pp.3-11
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• 2018