• Title/Summary/Keyword: Oxide Scale

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Nanomachining on Single Crystal Silicon Wafer by Ultra Short Pulse Electrochemical Oxidation based on Non-contact Scanning Probe Lithography (비접촉 SPL기법을 이용한 단결정 실리콘 웨이퍼 표면의 극초단파 펄스 전기화학 초정밀 나노가공)

  • Lee, Jeong-Min;Kim, Sun-Ho;Kim, Tack-Hyun;Park, Jeong-Woo
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.20 no.4
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    • pp.395-400
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    • 2011
  • Scanning Probe Lithography is a method to localized oxidation on single crystal silicon wafer surface. This study demonstrates nanometer scale non contact lithography process on (100) silicon (p-type) wafer surface using AFM(Atomic force microscope) apparatuses and pulse controlling methods. AFM-based experimental apparatuses are connected the DC pulse generator that supplies ultra short pulses between conductive tip and single crystal silicon wafer surface maintaining constant humidity during processes. Then ultra short pulse durations are controlled according to various experimental conditions. Non contact lithography of using ultra short pulse induces electrochemical reaction between micro-scale tip and silicon wafer surface. Various growths of oxides can be created by ultra short pulse non contact lithography modification according to various pulse durations and applied constant humidity environment.

Growth of Large Scale CdTe(400) Thin Films by MOCVD (MOCVD를 이용한 대면적 CdTe 단결정 박막성장)

  • Kim, Kwang-Chon;Jung, Kyoo-Ho;You, Hyun-Woo;Yim, Ju-Hyuk;Kim, Hyun-Jae;Kim, Jin-Sang
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.4
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    • pp.343-346
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    • 2010
  • We have investigated growth of CdTe thin films by using (As, GaAs) buffer layers for application of large scale IR focal plane arrays(IFPAs). Buffer layers were grown by molecular beam epitaxy(MBE), which reduced the lattice mismatch of CdTe/Si and prevented native oxide on Si substrates. CdTe thin films were grown by metal organic chemical deposition system(MOCVD). As a result, polycrystalline CdTe films were grown on Si(100) and arsenic coated-Si(100) substrate. In other case, single crystalline CdTe(400) thin film was grown on GaAs coated-Si(100) substrate. Moreover, we observed hillock structure and mirror like surface on the (400) orientated epitaxial CdTe thin film.

Improvement of Thermal Stability of Nickel Silicide Using Co-sputtering of Ni and Ti for Nano-Scale CMOS Technology

  • Li, Meng;Oh, Sung-Kwen;Shin, Hong-Sik;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.3
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    • pp.252-258
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    • 2013
  • In this paper, a thermally stable nickel silicide technology using the co-sputtering of nickel and titanium atoms capped with TiN layer is proposed for nano-scale metal oxide semiconductor field effect transistor (MOSFET) applications. The effects of the incorporation of titanium ingredient in the co-sputtered Ni layer are characterized as a function of Ti sputtering power. The difference between the one-step rapid thermal process (RTP) and two-step RTP for the silicidation process has also been studied. It is shown that a certain proportion of titanium incorporation with two-step RTP has the best thermal stability for this structure.

Fabrication of Nanoscale Structures using SPL and Soft Lithography (SPL과 소프트 리소그래피를 이용한 나노 구조물 형성 연구)

  • Ryu Jin-Hwa;Kim Chang-Seok;Jeong Myung-Yung
    • Journal of the Korean Society for Precision Engineering
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    • v.23 no.7 s.184
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    • pp.138-145
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    • 2006
  • A nanopatterning technique was proposed and demonstrated for low cost and mass productive process using the scanning probe lithography (SPL) and soft lithography. The nanometer scale structure is fabricated by the localized generation of oxide patterning on the H-passivated (100) silicon wafer, and soft lithography was performed to replicate of nanometer scale structures. Both height and width of the silicon oxidation is linear with the applied voltagein SPL, but the growth of width is more sensitive than that of height. The structure below 100 nm was fabricated using HF treatment. To overcome the structure height limitation, aqueous KOH orientation-dependent etching was performed on the H-passivated (100) silicon wafer. Soft lithography is also performed for the master replication process. Elastomeric stamp is fabricated by the replica molding technique with ultrasonic vibration. We showed that the elastomeric stamp with the depth of 60 nm and the width of 428 nm was acquired using the original master by SPL process.

High Temperature Oxidation Behavior of Mg-6%Al-1%Zn-1%CaO Alloys

  • Lee, Dong Bok;Kim, Min Jung
    • Journal of Surface Science and Engineering
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    • v.50 no.1
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    • pp.42-45
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    • 2017
  • The magnesium-base AZ61 alloy was cast while adding 1% CaO powder into the melt. It was hot extruded, and oxidized at $550-650^{\circ}C$ in air in order to study its microstructure and oxidation behavior. Initially added CaO powder reacted with Al in the melt to $Al_2Ca$ particles that aligned along the extrusion direction. The formed $Al_2Ca$ particles increased the oxidation resistance through forming the superficial CaO scale at the upper part of the thin MgO oxide scale.

A Study on Cleaning Processes for Ti/TiN Scales on Semiconductor Equipment Parts (반도체 장비 부품의 Ti/TiN 흡착물 세정 공정 연구)

  • 유정주;배규식
    • Journal of the Semiconductor & Display Technology
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    • v.3 no.2
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    • pp.11-15
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    • 2004
  • Scales, accumulated on some parts of semiconductor equipments such as sputters and CVD during the device fabrication processes, often lower the lifetime of the equipments and production yields. Thus, many equipment parts have be cleaned regularly. In this study, an attempt to establish an effective process to remove scales on the sidewall of collimators located inside the chamber of the sputter was made. The EDX analysis revealed that the scales were composed of Ti and TiN with the columnar structure. Through the trial-and-error experiments, it was found that the etching in the $HNO_3$:$H_2SO_4$:$H_2O$=4:2:4 solution for 5.5 hrs at $67^{\circ}C$, after the oxide removal in the HF solution, and the heat-treatment at $700^{\circ}C$ for 1 min., was the most effective process for the scale removal.

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Study of the Electrolytic Reduction of Uranium Oxide in LiCl-Li$_{2}$O Molten Salts with an Integrated Cathode Assembly

  • Park Sung-Bin;Seo Chung-seok;Kang Dae-Seung;Kwon Seon-Gil;Park Seong-Won
    • Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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    • v.3 no.2
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    • pp.105-112
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    • 2005
  • The electrolytic reduction of uranium oxide in a LiCl-Li$_{2}$O molten salt system has been studied in a 10 g U$_{3}$O$_{8}$ /batch-scale experimental apparatus with an integrated cathode assembly at 650$^{\circ}C$. The integrated cathode assembly consists of an electric conductor, the uranium oxide to be reduced and the membrane for loading the uranium oxide. From the cyclic voltammograms for the LiCl-3 wt$\%$ Li$_{2}$O system and the U$_{3}$O$_{8}$-LiCl-3 wt$\%$ Li$_{2}$O system according to the materials of the membrane in the cathode assembly, the mechanisms of the predominant reduction reactions in the electrolytic reactor cell were to be understood; direct and indirect electrolytic reduction of uranium oxide. Direct and indirect electrolytic reductions have been performed with the integrated cathode assembly. Using the 325-mesh stainless steel screen the uranium oxide failed to be reduced to uranium metal by a direct and indirect electrolytic reduction because of a low current efficiency and with the porous magnesia membrane the uranium oxide was reduced successfully to uranium metal by an indirect electrolytic reduction because of a high current efficiency.

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Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits

  • Song, Taigon;Lim, Sung Kyu
    • Journal of information and communication convergence engineering
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    • v.13 no.3
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    • pp.180-188
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    • 2015
  • As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

Initial oxidation behavior in High temperature of low carbonsteel containing small amount Ni element. (미량 Ni 함유 저 합금강의 고온초기 산화거동)

  • 손근수
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 1999.10a
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    • pp.179-184
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    • 1999
  • When the steel containing Si is oxidated in hi temperature, Re2O3, Red scale is made on the metal side as the spike phase, and this scale invasion into matrix. Therefore, it affects the feature, after rolling. It is reported that the role of Si is FeO/Fe2SiO4 eutectic compound, but Si can not affect pure iron independently. There must be Ni, then the spike phase can exist. Prominence and depression made by Ni that is necessity at the process to work iron. Therefore, in this study after the change of the amount of Ni in pure iron and steel and oxidation, the structure of the oxide and the surface, and the distribution of the elements were considered. In conclusion, at 100$0^{\circ}C$, 110$0^{\circ}C$, 120$0^{\circ}C$ the curves of oxidation weight are all S curves. Especially, in the beginning of oxidation as the amount of Ni increase, the amount of oxidation also increase. Practical steel has less oxidation than pure steel added Ni. There is much FeO in Fe-Ni alloy, compare to practical steel which has much Fe3O4. Especially, we could know considerable Ni was concentrated on the metal side in Fe-Ni alloy, practical steel. and the surface of the scale.

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Study on the Reduction of Forging Oxide Scale using Hydrogen (단조 산화스케일로부터 철계분말 제조 기술개발 연구)

  • Lee, Dong-Won;Yun, Jung-Yeul;Shin, Shun-Myung;Kim, In-Soo;Wang, Jei-Pil
    • Journal of Powder Materials
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    • v.20 no.3
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    • pp.174-179
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    • 2013
  • The study on the fabrication of iron powder from forging scales using hydrogen gas has been conducted on the effect of hydrogen partial pressure, temperature, and reactive time. The mechanism for the reduction of iron oxides was proposed with various steps, and it was found that reduction pattern might be different depending on temperature. The iron content in the scale and reduction ratio of oxygen were both increased with increasing reactive time at 0.1atm of hydrogen partial pressure. On the other hand, for over 30 minutes at 0.5 atm of hydrogen partial pressure, the values were found to be almost same. In the long run, iron metallic powder was obtained with over 90% of iron content and an average size of its powder was observed to be about $100{\mu}m$.