• Journal of Power Electronics
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• 제14권4호
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• pp.649-660
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• 2014

A novel non-isolated bidirectional soft-switching SEPIC/ZETA converter with reduced ripple currents is proposed and characterized in this study. Two auxiliary switches and an inductor are added to the original bidirectional SEPIC/ZETA components to form a new direct power delivery path between input and output. The proposed converter can be operated in the forward SEPIC and reverse ZETA modes with reduced ripple currents and increased voltage gains attributed to the optimized selection of duty ratios. All switches in the proposed converter can be operated at zero-current-switching turn-on and/or turn-off through soft current commutation. Therefore, the switching and conduction losses of the proposed converter are considerably reduced compared with those of conventional bidirectional SEPIC/ZETA converters. The operation principles and characteristics of the proposed converter are analyzed in detail and verified by the simulation and experimental results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 B
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• pp.1087-1089
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• 2003

This paper presents a method to reduce commutation torque ripple in a sensorless brushless DC motor drive without current sensors. To compensate the commutation torque ripple completely, the duration of commutation must be known. The proposed method measures the duration of commutation from terminal voltage waveforms, calculates a PWM duty ratio to suppress the commutation torque ripple from the output of speed controller, and applies the calculated PWM duty ratio only during the commutation. Experimental results show that vibrations are considerably reduced when the proposed method is applied to the sensorless brushless DC moter drive for air-conditioner compressor.

• 전자공학회논문지
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• 제52권6호
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• pp.50-56
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• 2015

본 논문에서는 모바일 응용에 적합한 고효율의 빠른 응답 특성을 가지는 히스테리틱 벅 변환기를 제안한다. 기존 히스테리틱 변환기의 문제점인 큰 출력 전압 리플과 작은 용량의 전력 인덕터 사용의 어려움을 삼각파 신호 발생기를 통해 해결하였다. 그리고 부하 전류에 따라 가변하는 스위칭 주파수를 PLL(Phase Locked Loop)구조를 사용하여 일정하게 함으로써 주변 IC에 미치는 EMI(Electro Magnetic Interference)잡음을 최소화 하였다. 이 회로는 BCDMOS 0.35um 2-poly 4-metal 공정으로 제작되었으며, 측정 결과 입력전압 3.7V, 출력전압 1.2V 부하 전류 50~500mA 범위에서 20mV 이하의 출력 전압 리플을 나타내며 170mA 이상의 부하 전류를 구동하는 경우 2MHz의 고정된 스위칭 주파수에서 동작하였다.

• Journal of Power Electronics
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• 제18권6호
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• pp.1729-1750
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• 2018

Voltage source inverters (VSIs) are widely used to drive induction motors in industry applications. The quality of output waveforms depends on the switching sequences used in pulse width modulation (PWM). In this work, all existing optimal space vector pulse width modulation (SVPWM) switching strategies are studied. The performance of existing SVPWM switching strategies is optimized to realize a tradeoff between quality of output waveforms and switching losses. This study generalizes the existing optimal switching sequences for total harmonic distortions (THDs) and switching losses for different modulation indexes and reference angles with a parameter called quality factor. This factor provides a common platform in which the THDs and switching losses of different SVPWM techniques can be compared. The optimal spatial distribution of each sequence is derived on the basis of the quality factor to minimize harmonic current distortions and switching losses in a sector; the result is the minimum ripple loss SVPWM (MRSLPWM). By employing the sequences from optimized switching maps, the proposed method can simultaneously reduce THDs and switching losses. Two hybrid SVPWM techniques are proposed to reduce line current distortions and switching losses in motor drives. The proposed hybrid SVPWM strategies are MRSLPWM 30 and MRSLPWM 90. With a low-cost PIC microcontroller (PIC18F452), the proposed hybrid SVPWM techniques and the quality of output waveforms are experimentally validated on a 2 kVA VSI based on a three-phase two-level insulated gate bipolar transistor.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 추계학술대회
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• pp.62-64
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• 2018

In two-stage single-phase inverters, inherent double line frequency component is present at both input and output of the front-end converter. Generally large electrolytic capacitors are required to eliminate the ripple. It is well known that the low frequency ripple shortens the lifespan of the capacitor hence the system reliability. However, the ripple can hardly be eliminated without the hardware combined with an energy storage device or a certain control algorithm. In this paper, a novel power-decoupling control method is proposed to eliminate the double line frequency ripple at the front-end converter of the DC/AC power conversion system. The proposed control algorithm is composed of two loop, ripple rejection loop and average voltage control loop and no extra hardware is required. In addition, it does not require any information from the phase-locked-loop (PLL) of the inverter and hence it is independent of the inverter control. In order to prove the validity and feasibility of the proposed algorithm a 5kW Dual Active Bridge DC/DC converter and a single-phase inverter are implemented, and experimental results are presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• ETRI Journal
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• 제37권5호
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• pp.961-971
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• 2015

This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a$0.11{\mu}m$ CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at $20{\mu}A$ to $200{\mu}A$ load current.

• 전력전자학회논문지
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• 제7권5호
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• pp.443-452
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• 2002

수 백 Watt 급의 통신용 장비 등에 적합하도록 고안된, 직렬 연결된 두 개의 트랜스포머를 갖는 새로운 위상천이 풀 브릿지 컨버터를 제시한다. 제안된 회로의 장점은 넓은 입력 범위를 가지며, 경부하에서도 스위치의 영전압 조건을 보다 쉽게 만족시킬 수 있다는 점, 그리고 작은 출력 변동율을 갖는다는 점 등이다. 뿐만 아니라, 직렬로 연결된 두 개의 트랜스포머가 번갈아 가면서 주 트랜스포머로서의 역할과 출력 인덕터로서의 역할을 함께 수행하므로, 출력측에서는 인덕터없이 필터링이 가능하게 되고, 따라서 고전력밀도의 컨버터를 제작할 수 있게 된다. 모드 해석과 대신호 모델링을 통한 설계식의 유도, 그리고 실험 결과를 보여줌으로써 제안된 컨버터를 검증한다.

• 전력전자학회논문지
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• 제4권1호
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• pp.66-72
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• 1999

본 논문은 고주파 공진형 PWM 인버터식 X-선 장치의 인버터에 단상과 3상 전파정류방식 및 PSU 전원을 연결시켰을 때 나타나는 단시간 출력특성에 대해 분석하였다. X-선의 선질은 X-선관에 입력되는 DC 전압 파형에 의존한다. DC 출력전압 파형은 DC 전압전원의 고조파 왜곡에 의해 영향을 받는다. 이러한 관전압 파형의 왜곡은 X-선 출력의 직선성, 재현성 및 출력선질을 저하시킨다. 따라서 본 논문에서는 DC 출력전압 파형과 세 가지 형식의 DC 입력전원 형식에 따른 출력선량을 비교하였고 이에 따른 실험결과를 검토하였다.

• 한국산업융합학회 논문집
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• 제22권3호
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• pp.373-379
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• 2019

Nowadays, the IoT portable electronic devices have become more useful and diverse, so they require various supply voltage levels to operate. This paper presents a DC-DC buck converter with pulse width modulation (PWM) for portable electronic devices. The proposed step-down DC-DC converter consists of passive elements such as capacitors, inductors, and resistors and an integrated chip (IC) for signal control to reduce power consumption and improves ripple voltage with the resolution. The proposed DC-DC converter is simulated and analyzed in PSPICE circuit design platform, and implemented on the prototype PCB board with a Texas Instruments LM5165 IC. The proposed buck converter is showed 92.6% of peak efficiency including a load current range of 4-10 mA, 3.29 mV of the voltage ripple at 5 V output voltage for the supply voltage 12 V. Measured and Simulated power efficiency are made good agreement with each other.