• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.21-27
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• 2008

This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.3 no.1
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• pp.18-25
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• 1978

The 1/f noise spectrum of short-circuited output drain current due to the Shockley-Read-Hal] recombination centers with a single lifetime in homogeneous nondegenerate MOS-field effcte transtors with n-type channel is calculated under the assumptions that the quasi-Fermi level for the carriers in each energy band can not be defined if we include the fluctuation for time varying quantities. and so 1/f noise is a majority carrier effect. Under these assumptions the derived 1/f noise in this paper show some essential features of the 1/f noise in MOS-field effect transistors. That is, it has no lowfrequency plateau and is proportionnal to the channel cross area A and to the driain bias voltage Vd and inversely proportional to the channel length L3 in MOS field effect transistors. This model can explain the discrepancy between the transition frequency of the noise spectrum from 1/f- response to 1/f2 and the frequency corresponding to the relaxation time related to the surface centers in p-n junction diodes. In this paper the results show that the functional form of noise spectrum is greatly influenced by the functional forms of the electron capture probability cn (E) and the relaxation time r (E) for scattering and the case of lattice scattering show to be responsible for the 4 noise in MOS fold effect transistors. So we canconclude that the source of 1/f noise is due to lattice scattering.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.14-21
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• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.613-622
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• 2013

In this paper, an inductive clamping class-E power amplifier has been tested for wireless power transmission at ISM band, 13.56 MHz. The implemented power amplifier is designed to operate stably without destroying power transistor in wireless power transmission system which basically keeps not to align between a transmitting antenna and a receiving antenna. The power amplifier is also designed to enhance harmonic filtering characteristic. The amplifier was tested with a DC supply voltage of 28 V and input power of 25 dBm at 13.56 MHz. The test results show the output power level of 43 dBm, the difference power level between fundamental frequency and second harmonic frequency of more than 55 dBc, the dc current consumption of 830 mA, and the high power-added efficiency of 85 %. Finally, the implemented power amplifier operated normally with 830 mA DC current consumption from 28 V source when the two antennas were aligned, and the power transmission was successful. But when the two antennas were not aligned, its DC current consumption automatically decreased down to 420 mA to protect the switching transistor.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.12
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• pp.7287-7291
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• 2014

A CDTA (current differencing transconductance amplifier) is an active building block for current mode analog signal processing with the advantages of high linearity and a wide frequency bandwidth. In addition, it can generate a stable voltage because all the differencing input current flows to the grounded devices. In this paper, a new small signal equivalent circuit is proposed to analyze a CDTA. The proposed small signal equivalent circuit provides greater precision in analyzing the magnitude and frequency response than its previous counterparts because it considers the parasitic components of the input, internal and output terminal. In addition, observations of the changes made in various devices, such as the resistor (Rz) confirmed that those devices heavily influence the characteristics of CDTA. The designed parameters of the proposed small signal equivalent circuit of the CDTA provides convenience and accuracy in the further design of analog integrated circuits. For verification purposes, a 2.5 MHz low pass filter was designed on the HSPICE simulation program using the proposed small signal equivalent circuit of CDTA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of Biosystems Engineering
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• v.25 no.2
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• pp.97-106
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• 2000

To develop the grain moisture meter using microwave free space transmission technique, a 10.5GHz microwave signal with the power of 11mW generated by an oscillar with a dielectric resonator is transmitted to an isolator and radiated from a transmitting $2{\times}2$ microstrip patch array antenna into the sample holder filled with the 12 to 26%w.b. of Korean Hwawung paddy rice. the microwave signal, attenuated through the grain with moisture, is collected by a receiving $2{\times}2$ microstrip patch array antenna and detected using a Shottky diode with excellent high frequency characteristic. A pair of light and simple microstrip patch array antenna for measurement of grain moisture content is designed and implemented on atenflon substrate with trleative dielectric constant of 2.6 and thickness of 0.54 by using Ensemble ver. 4.02 software. The aperture of microstrip patch arrays is 41 mm width and 24mm high. The characteristics of microstrip patch antenna such as grain. return loss, and bandwidth are 11.35dBi, -38dB and 0.35GHz($50^{\circ}$ at far-field pattern of E and H plane. The width of the sample holder is large enough to cover the signal between the antennas temperature and bulk density respectively. The calibration model for measurement of grain moisture content is proposed to reduce the effects of fluectuations in bulk density and temperature which give serious errors for the measurements . From the results of regression analysis using the statistically analysis method, the moisture content of grain samples (MC(%)) is expressed in terms of the output voltage(v), temperature (t), and bulk density of samples(${\rho}b$)as follows ;$$MC(%)\;=\;(-3.9838{\times}10^{-8}{\times}v^{3}+8.023{\times}10^{-6}{\times}v^{2}-0.0011{\times}v-0.0004{\times}t+0.1706){\frac{1}{{\rho}b}}{\times}100$ Its determination coefficient, standard error of prediction(SEP) and bias were found to be 0.9855, 0.479%w.b. and -0.0.369 %w.b. respectively between measured and predicted moisture contents of the grain samples.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.750-755
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• 2003

This paper proposes a new three-line balun. The equivalent circuit of the proposed three-line balun is presented, and impedance matrix［Z］of the equivalent circuit is derived from the relationship between the current and voltage at each port. The design equation for a given set of balun impedance at input and output ports is presented using［S］parameters, which is transferred fom impedance matrix,［Z］. To demonstrate the feasibility and validity of design equation, multi-layer ceramic(MLC) chip balun operated in the 2.4 GHz ISM band frequency is designed and fabricated by the use of the low temperature co-fired ceramic(LTCC) technology. By employing both the proposed new three-line balun equivalent circuit and multi-layer configuration provided by LTCC technology, the 2012 size MLC balun is realized. Measured results of the multi-layer LTCC three-line balun match well with the full-wave electromagnetic simulation results, and measured in band-phase and amplitude balances over a wide bandwidth are excellent. This proposed balun is very easily applicable to multi-layer structure using LTCC as shown in the paper, and also can be realized with microstrip lines on PCB. This distinctive performance is very favorable for wireless communication systems such as wireless LAN(Local Area Network) and Bluetooth applications.

• Journal of Sensor Science and Technology
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• v.5 no.4
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• pp.17-24
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• 1996

Planar multi-junction thermal converters were fabricated for precise measurements of the ac voltage and current by an ac-dc transfer method. A heater and a thermocouple array were fabricated onto a sandwiched membrane, $Si_{3}N_{4}$ (200 nm) / $SiO_{2}$ (400 nm) / $Si_{3}N_{4}$ (200 nm), a thickness of $0.8\;{\mu}m$ and a size of $2{\times}4\;mm^{2}$, which is supported by a surrounding frame. The NiCr heater is located at the center of the membrane vertically. Hot junctions of $48{\sim}156$ pairs of thermocouples (Cu-CuNi44) are located near or onto the heater, and cold junctions are located onto the silicon frame. Output of the thermal converters for 10 mA dc input was $76\;mV{\sim}382\;mV$ dependent on a model, and short term stability of the outputs was ${\pm}5{\sim}15\;ppm$/ 10 min with 5 mA dc input. Responsivity in air was in the range of $3.9{\sim}14.5V/W$. Responsivity of the model BF48 in air which has 48 thermocouples was 2 times or greater than that of 3 dimensional multi-junction thermal converter in vacuum which has 56 thermocouples. AC-DC transfer differences with an input of 10 mA or less were less than ${\pm}1\;ppm$ in the frequency range from 5 Hz to 2 kHz, and about $2{\sim}3\;ppm$ at 5 kHz and 10 kHz.