• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.38-45
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• 2021

The photovoltaic module has the characteristic of changing its output characteristics depending on the amount of radiation and temperature, where the arrays that connect them in series and parallel also have the same characteristics. These characteristics require the MPPT technique to find the maximum power point. Existing P&O and IncCond cannot find the global maximum power point (GMPP) for partial shading. Moreover, in the case of Improved-GMPPT and Enhanced Search-Skip-Judge-GMPPT, GMPP due to partial shading can be found, but the variation in the open voltage during temperature fluctuations will affect the operation of the Skip and will not be able to perform accurate MPPT operation. In this study, we analyzed the correlation between voltage, current, and power under solar module and array conditions. We also proposed a technique to find the maximum power point even for temperature fluctuations using not only the amount of radiation but also the temperature coefficient. The proposed control technique was verified through simulations and experiments by constructing a 2.5 kW single-phase solar power generation system.

• Journal of Sensor Science and Technology
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• v.11 no.2
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• pp.67-76
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• 2002

We have presented a 2-dimensional fluxgate sensor with ferrite core, excitation, and pick-up coil. This fluxgate sensor system consists of a sensing element, driving circuits for excitation coil and signal processing for detecting second harmonic frequency component which is proportional to the DC magnetic to be measured. The sensor core is excited by a square waveform of voltage through the excitation coil of 80 turns. The second harmonic output of pick-up coil(x and y axis: 100 turns) is measured by FFT spectrum analyzer. This result is compared with output of PSD(phase sensitive detector) unit for detecting the second harmonic component. The measured maximum sensitivity is about 1580 V/T at driving frequency of 1.5 kHz and excitation current of 2 App. The nonlinearity of this system is measured about 2.3%(PSD) and about 1%(second harmonics of the pick-up). The angle error of the system is ${\pm}2$ %/FS.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.6
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• pp.117-125
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• 2007

Recently, a fuel cell with low voltage and high current output characteristics is remarkable for new generation system. It needs both a DC-DC step-up converter and DC-AC inverter to be used in fuel cell generation system. Therefor, this paper, consists of an isolated DC-DC converter to boost the fuel cell voltage 380[VDC] and a PWM inverter with LC filter to convent the DC voltage to single-phase 220[VAC]. Expressly, The fuel cell system which it proposes DC-DC the efficient converter used PWM the phase transient control law and it depended to portion resonance ZVS switching, loss peek voltage and electric current of realization under make schedule, switching frequency anger and the switch reduction. And mind benevolence it sprouted 2 in stop circuit and it added and a direct current voltage and the electric current where the ingredient is reduced in load side ripple stable under make whom it will be able to supply. Besides the efficiency of 92[%]is obtained over the wide output voltage regulation ranges and load variations. Also, under make over together the result leads simulation and test, the propriety confirmation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.11-17
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• 2001

In this paper, we propose a polarity decision carrier recovery algorithm for high order QAM(Quadrature Amplitude Modulation), which has robust and large frequency acquisition performance in the high order QAM modem. The proposed polarity decision PD(Phase Detector) output and its variance characteristic are mathematically derived and the simulation results are compared with conventional DD(Decision-Directed) method. While the conventional DD algorithm has linear range of $3.5^{\circ}{\sim}3.5^{\circ}$, the proposed polarity decision PD algorithm has linear range as large as $-36^{\circ}{\sim}36^{\circ}$ at ${\gamma}-17.9$. The conventional DD algorithm can only acquire offsets less than ${\pm}10\;KHz$ in the case of the 256 QAM while an analog front-end circuit generally can reduce the carrier-frequency offset down to only ${\pm}100\;KHz$. Thus, in this case additional AFC or phase detection circuit for carrier recovery is required. But by adopting the proposed polarity decision algorithm, we can find the system can acquire up to ${\pm}300\;KHz$at SNR = 30dB without aided circuit.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of Advanced Navigation Technology
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• v.12 no.3
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• pp.208-214
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• 2008

With the development of the automobile industry, technologies for parts of an automobile with more convenient functions have progressed, but the manual clutch developed at the first phase of inventing means of transport still remains at the early stage of the automatic transmission despite numerous research and efforts. The traditional automatic transmission is mainly used in small cars and personal RV vehicles that include the slipped clutch disk. However, this research seeks an innovative technology that can be applied to all types of transportation operating the clutch, such as small cars, large vehicles, farm machines and vessels. In order to accurately decide the joint timing of the clutch disk according to the output of engine power that differs depending on driving conditions of vehicles, and to apply the half clutch state which frequently occurs in the manual transmission, the rpm of the engine can be used as the base to decide the joint timing of the clutch disk. This research has developed an electronic clutch module that can transmit the engine power by moving and jointing the clutch disk as much as the engine rpm increases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2391-2396
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• 2010

The power-controlled six-port element that can control the local oscillator signal power and receiving RF signal power was designed and implemented in this paper. The direct conversion six-port element configuration was proposed, which provides the constant six-port output power by controlling the six-port input power with various signal strength. The direct conversion six-port element protects the power detector element of six-port receiver from the saturation status and compensates the transmission performance degradation. For implementation of power-controlled six-port element, the power-controlled six-port element including the power controller was analyzed. The implemented power-controlled six-port element shows the power control capability of 36 dB and gain imbalance of about 1.6 dB, phase imbalance of about $4^{\circ}$ in the frequency range of 1.69 GHz. The measured results show the good performance as direct conversion front-end element.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2747-2754
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• 2012

This thesis explains the development of multiple LCD system with the additional function to maximize the utilization of PC contents. The newly developed system is composed of host LCD and slave LCD. Host LCD decodes and outputs the image and voice of NTSC, PAL, SECAM signals. It also converts the decoded signals into LVDS signals before transmitting them to slave LCD stage. In addition, the installation of CF Memory and USB Memory helps display multi-media data. Unlike the host LCD, since not including the tuner and memory part, the slave LCD can't receive TV signals and play video signals. It only has the function to receive LVDS image signals and display on a LCD panel. This newly developed multi-LCD system has competitiveness in various aspects. With its simple structure, the failure rate, price and display power are relatively low due to its simplification of the control part. It has price and functional competitiveness as the product whose host LCD can control the entire slave LCD in terms of channel, volume, and video output.

• Journal of the Earthquake Engineering Society of Korea
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• v.3 no.4
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• pp.47-60
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• 1999

The stability and efficiency of structural control systems depend on the accuracy of mathematical model of the system to be controlled. In this study, state equation models of a small scale test structure and an AMD(active mass damper) are obtained separately using OKID(observer/Kalman filter identification) which is a time domain system identification method. The test structure with each floor acceleration as outputs is identified for two inputs - the ground acceleration and the acceleration of the moving mass of AMD relative to the installation floor - individually and the two identified state equation models are integrated into one by model reduction method. The AMD is identified with the motor control signal as an input and the relative acceleration of the moving mass as an output, and it is shown that the identified model has large damping ratio and phase shift. The transfer functions and the time histories reconstructed from the identified models of the test model and the AMD match well with those measured from the experiment.