• 폴리머
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• 제30권3호
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• pp.253-258
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• 2006

4 종류의 n형 유기 반도체 물질 F16CuPC, NTCDA, PTCDA, PTCDI C-8을 사용하여 ITO/n형 활성물질/Al gate/n형 활성물질/Al으로 구성되는 세로형 유기 박막트랜지스터를 제작하였다. 캐리어 이동도의 차이를 갖는 유기 물질의 종류와 유기 박막층의 두께 조절에 따른 유기 박막트랜지스터의 전류전압(I-V) 특성 및 전류의 온오프비에 미치는 영향을 조사하였다. PTCDI C-8을 사용한 세로형 유기 박막트랜지스터에서 낮은 구동전압과 높은 스위칭 특성을 보였다. ITO/PEDOT-PSS/P3HT/F16CuPc/Al gate/F16CuPc/Al으로 구성되는 발광트랜지스터를 제작하였고, 20 V에서 최고 0.054의 양자 효율을 나타내었다.

• 폴리머
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• 제38권2호
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• pp.188-192
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• 2014

본 연구에서는 용해도가 낮은 용매에 dipping하는 방법을 이용하여 고분자 반도체 박막의 분자규칙도를 쉽게 향상시켰다. Poly(3-hexylthiophene)(P3HT)의 구조적, 광학적, 전기적 특성은 dipping 용매의 용해도와 dipping 시간에 따라 크게 영향을 받았다. 특히 methylene chloride 용매에 P3HT 박막을 dipping한 뒤 dipping 시간을 조절하여 고분자 박막의 분자규칙도를 효과적으로 증가시켰다. 분자규칙도와 전기적 특성의 관계를 고려하여 적절한 용매선택과 dipping 시간을 최적화할 수 있었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.182-183
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• 2008

We fabricated a pentacene thin film transistor with Poly-vinylalcohol (PVA) as a dielectric. And we used Poly(9-vinylcarbazole) (PVK) as a buffer layer to improve the electrical characteristics. PVK is a material used often host material for OLED device, as it has good film forming properties, large HOMO-LUMO(highest occupied molecular orbital-lowest unoccupied molecular orbital) bandgap. The performance of a OTFT device with PVA gate dielectric was improved by using the PVK. Field effect mobility, threshold voltage, and on-off current ratio of device with PVK layer were about 0.6 $cm^2$/Vs, -17V, and $5\times10^5$, respectively.

• Bulletin of the Korean Chemical Society
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• 제34권4호
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• pp.1170-1174
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• 2013

Benzodithiophene based organic semiconducting polymer was designed and synthesized by stille coupling reaction. The structure of polymer was confirmed by NMR and IR. The weight average molecular weight ($M_w$) of polymer was 8,400 using GPC with polydispersity index of 1.4. The thermal, optical and electrochemical properties of polymer were characterized by TGA and DSC, UV-vis absorption and cyclic voltammetry. OTFT device using PBDT-10 exhibited the mobility of $7.2{\times}10^{-5}\;cm^2\;V^{-1}\;s^{-1}$ and $I_{on}/I_{off}$ of $2.41{\times}10^3$. The film morphology and crystallinity of PBDT-10, was studied using AFM and XRD.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1220-1224
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• 2007

The effects of plasma damages to the organic thin film transistor (OTFT) during the fabrication process are investigated; metal deposition process on the organic gate insulator by plasma sputtering mainly generates the process induced damages of bottom contact structured OTFTs. For this study, various deposition methods (thermal evaporation, plasma sputtering, and neutral beam based sputtering) and metals (gold and Indium-Tin Oxide) have been tested for their damage effects onto the Poly 4-vinylphenol(PVP) layer surface as an organic gate insulator. The surface damages are estimated by measuring surface energies and grain shapes of organic semiconductor on the gate insulator. Unlike thermal evaporation and neutral beam based sputtering, conventional plasma sputtering process induces serious damages onto the organic surface as increasing surface energy, decreasing grain sizes, and degrading TFT performance.

• 한국전기전자재료학회논문지
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• 제19권6호
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• pp.563-567
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• 2006

Indium tin oxide (ITO) used as an electrode in organic light emitting diodes (OLEDs) and organic thin film transistors (OTFTs) was modified by a self-assembled monolayer (SAM). For device fabrication, surface of the ITO was modified by immersion in a solution including various phosphonic acid at room temperature in order to increase work function of an electrode. The work function of ITO with SAM was measured by Kelvin probe. Work function increase of 0.88 eV was observed in ITO with various SAM. Therefore, ohmic contact is achieved in an interface between ITO and organic semiconductors (pentacene). We analyzed the origin of work function increase of ITO with SAM by X-ray photoelectron spectroscopy. We confirmed that increase of oxygen bonding energy attributed to increase the work function of ITO. These results suggested that ITO with the SAM gives a high possibility for high performance of OLEDS and OTFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.421-427
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• 2009

We successfully fabricated 4.7-inch organic thin film transistors array with $640{\times}480$ pixels on flexible substrate. All the processes were done by photolithography, spin coating and ink-jet printing. The OTFT-Electrophoretic (EP) pixel structure, based on a top gate OTFT, was fabricated. The mobility, ON/OFF ratio, subthreshold swing and threshold voltage of OTFT on flexible substrate are: 0.01 ^2/V-s, 1.3 V/dec, 10E5 and -3.5 V. After laminated the EP media on OTFT array, a panel of 4.7-inch $640{\times}480$ OTFT-EPD was fabricated. All of process temperature in OTFT-EPD is lower than $150^{\circ}C$. The pixel size in our panel is $150{\mu}m{\times}150{\mu}m$, and the aperture ratio is 50 %. The OTFT channel length and width is 20 um and 200um, respectively. We also used OTFT to drive EP media successfully. The operation voltages that are used on the gate bias are -30 V during the row data selection and the gate bias are 0 V during the row data hold time. The data voltages that are used on the source bias are -20 V, 0 V, and 20 V during display media operation.

• 대한전자공학회논문지SD
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• 제44권11호
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• pp.15-19
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• 2007

OTFTs (Organic Thin Film Transistors)의 구동에 있어, 게이트 절연막 표면과 채널의 계면상태가 소자의 전기적 특성에 큰 영향을 미치게 된다. OTS(Octadecyltrichlorosilane)등과 같은 습식 SAM(Self Assembly Monolayer)를 이용하거나, $O_2$ Plasma와 같은 건식 표면 처리등 여러 표면 처리법에 대한 연구가 진행되고 있다. 본 논문에서는 pentacene을 진공 증착하기 전에 게이트 절연막을 $O_2$ plasma와 Ar ion beam을 이용하여 건식법으로 전처리 한 후 표면 특성을 atomic force microscope (AFM) and X-ray photoelectron spectroscopy (XPS)를 사용하여 비교 분석하였고, 각 조건으로 OTFT를 제작하여 전기적 특성을 확인하였다. Ar ion beam으로 표면처리 했을 때, $O_2$ plasma처리했을 때 보다 향상된 on/off ratio 전기적 특성을 얻을 수 있었다. 표면 세정을 위하여 $O_2$ plasma 처리시 $SiO_2$ 표면의 OH-기와 반응하여 oxide trap density가 높아지게 되고 이로 인하여 off current가 증가하는 문제가 발생한다. 불활성 가스인 Ar ion beam 처리를 할 경우 게이트 절연막의 세정 효과는 유지하면서, $O_2$ Plasma 처리했을 때 증가하게 되는 계면 trap을 억제할 수 있게 되어, mobility 특성은 동등 수준으로 유지하면서 off current를 현저하게 줄일 수 있게 되어, 결과적으로 높은 on/off ratio를 구현할 수 있다는 것을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1103-1106
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• 2006

We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.