• ETRI Journal
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• 제39권3호
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.

• 대한지역사회작업치료학회지
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• 제9권2호
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• pp.13-22
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• 2019

목적 : 본 연구는 정상노화 과정에 따른 일화기억 저하 양상을 일화기억의 하위요소인 사물, 공간위치, 시간순서 기억을 중심으로 파악하고자 하였다. 연구방법 : 20대부터 80대 이상까지의 건강한 젊은 성인과 노인 77명이 본 연구에 참여하였으며, 일화기억을 평가하기 위한 컴퓨터 인지과제를 수행하였다. 인지과제는 사물, 공간위치, 시간순서 기억을 각각 평가하기 위한 세 가지 항목으로 구성되어 있었으며, 주변에서 흔하게 볼 수 있는 사진 10장을 이용하여 검사를 진행하였다. 사진 10장을 본 이후에 사진 속의 사물의 종류, 사물의 위치, 사진이 제시된 순서를 물어보는 과정을 통해 평가를 진행하였으며, 각 하위검사의 정답률을 연령대별로 분석하였다. 결과 : 연구 결과, 사물과 공간위치 기억은 정상노화에 큰 영향을 받지 않는 반면, 시간순서 기억은 정상노화 과정 속에서 큰 폭으로 저하되는 것을 알 수 있었다. 세부적으로 살펴보면 시간순서 기억은 40대 이상부터 20~30대에 비해 유의한 저하가 발생하는 것을 관찰할 수 있었고 80대 이후에는 사물 기억이 가장 높은 것으로 확인되었다. 즉 정상 노화 과정에 따라 시간순서 기억이 가장 먼저 감소되고 사물 기억이 가장 마지막에 저하되는 것을 확인하였다. 결론 : 본 연구는 정상노화 과정에 따른 일화기억의 하위요소별 저하 양상을 제시하였다. 사물 기억에 초점을 맞춘 기존의 신경심리학적 검사들을 통해 제한적으로 확인하였던 공간위치와 시간순서 기억의 저하 양상을 세부적으로 확인할 수 있었다. 본 연구 결과는 정상노화에 따른 일화기억의 저하에서 벗어난 일화기억의 손상을 선별하는데 도움이 될 것이며, 정상노인에게 시행되는 예방적인 인지 중재에 공간위치와 시간순서 기억의 훈련이 포함되어야 할 근거를 제시한다.

• 국제물리치료학회지
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• 제9권4호
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• pp.1591-1595
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• 2018

The number of healthy older adults is rapidly increasing recently owing to the increase of the elderly population. Therefore, programs for improving the cognitive functions of these healthy seniors are actively being expanded. This study aimed to prevent the decline of cognitive function due to aging by applying a program enhancing cognitive functions to healthy older adults. The objective of this study was to evaluate the effects of Korean computer-based cognitive rehabilitation program (CoTras), which is commonly used in cognitive therapy for the aging, on the memory of the elderly. The subjects had scored at least 24 points in MMSE-K. CoTras was applied once a week (30 minutes) for one month. Electronic pegboard programs were used as an evaluation tool: order memory (difficulty=low) and location memory (difficulty=medium). The order and location memories were compared before and after the intervention. The Wilcoxon signed rank-sum test was used for the study at the significance level of ${\alpha}=.05$. The results showed that CoTras significantly improved order memory and location memory. Therefore, CoTras can be applied to the healthy elderly for improving that memory improvement training has a positive impact on healthy older adults result in the development of memory enhancement programs can be expanded in the future.

• Journal of Information Processing Systems
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• 제14권2호
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• pp.499-509
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• 2018

Recently, hybrid transactional memory (HyTM) has gained much interest from researchers because it combines the advantages of hardware transactional memory (HTM) and software transactional memory (STM). To provide the concurrency control of transactions, the existing HyTM-based studies use a bloom filter. However, they fail to overcome the typical false positive errors of a bloom filter. Though the existing studies use a global lock, the efficiency of global lock-based memory allocation is significantly low in multi-core environment. In this paper, we propose an efficient hybrid transactional memory scheme using near-optimal retry computation and sophisticated memory management in order to efficiently process transactions in multi-core environment. First, we propose a near-optimal retry computation algorithm that provides an efficient HTM configuration using machine learning algorithms, according to the characteristic of a given workload. Second, we provide an efficient concurrency control for transactions in different environments by using a sophisticated bloom filter. Third, we propose a memory management scheme being optimized for the CPU cache line, in order to provide a fast transaction processing. Finally, it is shown from our performance evaluation that our HyTM scheme achieves up to 2.5 times better performance by using the Stanford transactional applications for multi-processing (STAMP) benchmarks than the state-of-the-art algorithms.

• 대한치매학회지
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• 제22권4호
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• pp.148-157
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• 2023

Background and Purpose: Episodic memory is a system that receives and stores information about temporally dated episodes and their interrelations. Our study aimed to investigate the relevance of episodic memory to time perception, with a specific focus on simultaneity/order judgment. Methods: Experiment 1 employed the simultaneity judgment task to discern differences in time perception between patients with mild cognitive impairment or dementia, and age-matched normals. A mathematical analysis capable of estimating subjects' time processing was utilized to identify the sensory and decisional components of temporal order and simultaneity judgment. Experiment 2 examined how differences in temporal perception relate to performance in temporal order memory, in which time delays play a critical role. Results: The temporal decision windows for both temporal order and simultaneity judgments exhibited marginal differences between patients with episodic memory impairment, and their healthy counterparts (p = 0.15, t(22) = 1.34). These temporal decision windows may be linked to the temporal separation of events in episodic memory (Pearson's ρ = -0.53, p = 0.05). Conclusions: Based on our findings, the frequency of visual events accumulated and encoded in the working memory system in the patients' and normal group appears to be approximately (5.7 and 11.2) Hz, respectively. According to the internal clock model, a lower frequency of event pulses tends to result in underestimation of event duration, which phenomenon might be linked to the observed time distortions in patients with dementia.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.157-169
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• 2013

Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.

• 한국산학기술학회논문지
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• 제5권5호
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• pp.389-394
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• 2004

이 논문에서는 플래시 메모리의 특성에 따른 메모리 재활용 방법론을 제안하여 비용을 감소시키면서 동시에 성능의 감소를 방지하는 목적을 만족시키고자 한다. 새로운 방법론은 재활용 대상 메모리 세그먼트 공간을 K 개의 하부 공간으로 분할하여 전체 검색을 대신 부분 검색을 실행하여 비용의 최소화를 추구한다. 아울러, 새로운 메모리 공간 배정 결정 시 전체 플래시 메모리 공간의 균등 소거에 대한 개선책을 제안한다. 제안된 방법론의 최적화를 위하여 하부 공간 분할 크기를 실험을 통해 취득 하였다. 실험적 자료는 제안된 방법론이 기존의 방법론과 비교하였을 교 비용은 감소하고 성능은 개선되는 것을 예시한다. 또한, 실험을 통해 메모리 공간 배정이 메모리 공간의 균등 소거에 많은 영향을 미친다는 사실을 확인할 수 있다.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2012년도 추계학술대회
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• pp.52-53
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• 2012

Belief propagation (BP) is a commonly used global energy minimization algorithm for solving stereo matching problem in 3D reconstruction. However, it requires large memory bandwidth and data size. In this paper, we propose a novel memory-efficient algorithm of BP in stereo matching on the Graphics Processing Units (GPU). The data size and transfer bandwidth are significantly reduced by storing only a part of the whole message. In order to maintain the accuracy of the matching result, the local messages are reconstructed using shared memory available in GPU. Experimental result shows that there is almost an order of reduction in the global memory consumption, and 21 to 46% saving in memory bandwidth when compared to the conventional algorithm. The implementation result on a recent GPU shows that we can obtain 22.8 times speedup in execution time compared to the execution on CPU.

• International Journal of Internet, Broadcasting and Communication
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• 제13권3호
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• pp.104-108
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• 2021

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

• Industrial Engineering and Management Systems
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• 제9권3호
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• pp.227-241
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• 2010

A memory module industry's supply chain usually consists of multiple manufacturing sites and multiple distribution centers. In order to fulfill the variety of demands from downstream customers, production planners need not only to decide the order allocation among multiple manufacturing sites but also to consider memory module industrial characteristics and supply chain constraints, such as multiple material substitution relationships, capacity, and transportation lead time, fluctuation of component purchasing prices and available supply quantities of critical materials (e.g., DRAM, chip), based on human experience. In this research, a directed graph-based supply network planning (DGSNP) model is developed for memory module industry. In addition to multi-site order allocation, the DGSNP model explicitly considers production planning for each manufacturing site, and purchasing planning from each supplier. First, the research formulates the supply network's structure and constraints in a directed-graph form. Then, a proposed genetic algorithm (GA) solves the matrix form which is transformed from the directed-graph model. Finally, the final matrix, with a calculated maximum profit, can be transformed back to a directed-graph based supply network plan as a reference for planners. The results of the illustrative experiments show that the DGSNP model, compared to current memory module industry practices, determines a convincing supply network planning solution, as measured by total profit.