• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• Communications for Statistical Applications and Methods
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• v.22 no.2
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• pp.137-146
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• 2015

Singh (2013) considered the dual problem to the calibration of design weights to obtain a new generalized linear regression estimator (GREG) for the finite population total. In this work, we have made an attempt to suggest a way to use the dual calibration of the design weights in case of multi-auxiliary variables; in other words, we have made an attempt to give an answer to the concern in Remark 2 of Singh (2013) work. The same idea is also used to generalize the GREG estimator proposed by Deville and S$\ddot{a}$rndal (1992). It is not an easy task to find the optimum values of the parameters appear in our approach; therefore, few suggestions are mentioned to select values for such parameters based on a random sample. Based on real data set and under simple random sampling without replacement design, our approach is compared with other approaches mentioned in this paper and for different sample sizes. Simulation results show that all estimators have negligible relative bias, and the multivariate case of Singh (2013) estimator is more efficient than other estimators.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.182-187
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• 1988

Hot carrier induced device degradation characteristics under DC bias stress have been investigated in n-MOSFETs with channel length of 1.2,1.8 um, and compared with those of LDD structure device with same channel length. Based on these results, the device lifetime in normal operating bias(Vgs=Vds=5V) is evaluated. The lifetimes of conventional and LDD n-MOSFET with channel length of 1.2 um are estimated about for 17 days and for 12 years, respectively. The degradation rate of LDD n-MOSFET under the same stress is the lowest at n-region implnatation dose of 2.5E15 cm-\ulcorner while the substrate current is the lowest at the dose of 1E13cm-\ulcorner Thses results show that the device degradation characteristics are basic measurement parameter to find optimum process conditions in LDD devices and evaluate a reliability of sub-micron device.

• Proceedings of the Korean Nuclear Society Conference
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• 1995.05a
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• pp.973-979
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• 1995

The input equivalent noise charge (ENC) of hydrogenated amorphous silicon radiation detector diodes was measured and analyzed. The noise sources of amorphous silicon diodes were analyzed into three sources; shot noise, flicker noise and thermal noise from the contact resistance. By comparing the measured ENC with the calculated signal charge in uniform generation case, the signal-to-noise ratio (S/N) for the sample diodes is estimated as a function of the detector bias and the shaping time of Gaussian pulse shaper. The maximum S/N occurred at the bias level just above the full depletion voltage for shaping time of 2∼3 ${\mu}$sec. The developed method is useful in optimum design or amorphous silicon p-i-n diodes for charged particulate radiation spectroscopy.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.6
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.

• Journal of the Korean Ceramic Society
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• v.40 no.9
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• pp.886-890
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• 2003

The etching characteristics of a LiNbO$_3$ single crystal have been investigated using helicon wave plasma source with bias power and the mixture of CF$_4$, HBr, SF$_{6}$ gas parameters. The etching rate of LiNbO$_3$ with etching parameters was evaluated by surface profiler. The etching surface was evaluated by Atomic Force Microscopy (AFM). The surface morphology of the etched LiNbO$_3$ changed with bias power and the mixture of CF$_4$/Ar/Cl$_2$, HBr/Ar/Cl$_2$, and SF$_{6}$/Ar/Cl$_2$ parameters. Optimum etching conditions, considering both the surface flatness and etch rate were determined.

• Journal of the Korean Vacuum Society
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• v.7 no.2
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• pp.161-168
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• 1998

Reactive ion etching process for InGaAs/InP using the CH4/H2 high density inductively coupled plasma was investigated. The experimental design method proposed by Taguchi was utilized to cover the whole parameter range while maintaining reasonable number of actual experiments. Results showed that the ICP power mainly affects surface roughness and verticality of the sidewall, bias power does etch rate and verticality, CH4 gas concentraion does the verticality and etch rate, and the distance between the induction coil and specimen mostly affects the surface roughness. It was also observed that the chamber pressure is the dominant parameter for the etch rate and verticality of the sidewall. The optimum condition was ICP power 700W, bias power 150 W, 15% $CH_4$, 7.5 mTorr, and 14 cm distance, resulting in about 3 $\mu\textrm{m}$/hr etch rate with smooth surfaces and vertical mesa sidewalls.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.456-459
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• 1999

This paper presents about EL(electroluminescent) driver with inverter. Inverter is composited two FET to increase safety output voltage. As result this study, the optimum operating condition of inverter is that the gate bias frequency of FET equal two resonant frequency of circuit. It shows to ideal sinusoidal output wave. Finally, EL sampler(15cm$\times$15cm) gain 2.6 [lux] with 1cm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.612-619
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• 1990

In this paper, a design method of optical FSK transmitter is described using LD-FM circuit model. In the design of optical FSK transmitter, an optimum bias current was chosen using LD-FM circuit model, and an unequalized FM transfer function was determined at this current. The equalizers that can make this transfer function uniform were designed by use of a simple passive network. For the designed optical FSK transmitter, the pulse-transient and small-signal frequency-deviation responses were simulated and discussed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1733-1739
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• 1997

An ultra-compact milimeter-wave broadband MMIC amplifier was designed using a direct-coupled topology combined with optimum feedback design. Significant reductionin the chip size was possible by employing the direct-coupled topology. Bias resistors required for the direct-coupled topology were also used as feedback elements. Feedback was optimized for millimeter-wave frequencies using reactive elements. The fabricated MMIC amplifier was realized in a chip size of 0.8mm$^{[-992]}$ and showed gains higher than 8 dB from 12 to 44 GHz. An output power of 30mW was achieved at 44 GHz with a drain efficiency of 10%.