• Transactions on Electrical and Electronic Materials
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• 제9권6호
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• pp.260-264
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• 2008

The operational characteristics of superconducting amplifier using vortex flux flow were analyzed from an equivalent circuit in which its current-voltage characteristics for the vortex motion in YBCO microbridge were reflected. For the analysis of operation as an amplifier, dc bias operational point for the superconducting amplifier is determined and then ac operational characteristics for the designed superconducting amplifier were investigated. The variation of transresistance, which describes the operational characteristics of superconducting amplifier, was estimated with respect to conditions of dc bias. The current and the voltage gains, which can be derived from the circuit for small signal analysis, were calculated at each operational point and compared with the results obtained from the numerical analysis for the small signal circuit. From our paper, the characteristics of amplification for superconducting flux flow transistor (SFFT) could be confirmed. The development of the superconducting amplifier applicable to various devices is expected.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.278-283
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• 2013

This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{\mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{\mu}W$ and chip area is $75{\mu}m{\times}90{\mu}m$.

• 한국전기전자재료학회논문지
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• 제15권9호
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• pp.743-749
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• 2002

A 1.5V 70㏈ 100MHz CMOS class-AB complementary operational amplifier is presented. For obtaining the high gain and the high unity gain frequency, the input stage of the amplifier is designed with rail-to-rail complementary differential pairs which are symmetrically parallel-connected with the NMOS and the PMOS differential input pairs, and the output stage is designed to the rail-to-rail class-AB output stage including the elementary shunt stage technique. With this design technique for output stage, the load dependence of the overall open loop gain is improved and the push-pull class-AB current control can be implemented in a simple way. The designed operational amplifier operates perfectly on the complementary mode with 180$^{\circ}$ phase conversion for 1.5V supply voltage, and shows the push-pull class-AB operation. In addition, the amplifier shows the DC open loop gain of 70.4 ㏈ and the unity gain frequency of 102 MHz for $C_{L=10㎊∥}$ $R_{L=1㏁}$ Parallel loads. When the resistive load $R_{L}$ is varied from 1 ㏁ to 1 ㏀, the DC open loop gain of the amplifier decreases by only 2.2 ㏈.a$, the DC open loop gain of the amplifier decreases by only 2.2 dB.

• 대한전자공학회논문지
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• 제23권4호
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• pp.477-483
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• 1986

This paper studies the design of a CMOS operational amplifier for the switched capacitor filter by computer simulation, and presents the results of measurement. The operational amplifier composed of two stages is fabricated in the CMOS digital process. The DC voltage gain of the operational amplifier is 66dB, and the unity gain bandwidth is 833kHz. These results satisfy the performance requirmance requirements for the operational amplifier of the switched capacitor filter.

• 센서학회지
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• 제1권1호
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• pp.13-21
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• 1992

Hall 소자 및 OP-앰프의 장점을 동시에 살린 'Hall 소자를 이용한 자기연산증폭기'를 구성하였다. 이 자기연산증폭기는 높은 입력임피던스 회로와 두 신호의 차 신호를 하나의 신호로 변환하는 회로를 반드시 필요로 하고, 또 이것을 연산처리하기 위해 궤환 입력을 받아 들일 수 있어야 한다. 본 논문에서는 이러한 특성을 만족하는 새로운 '두 신호의 차 신호를 하나의 신호로 변환하는 연산증폭기(DSCOP)'를 제안하였다. 그리고 제안된 DSCOP와 Hall 소자를 이용하여 자기연산증폭기를 설계하여 그 특성을 시뮬레이션 하였으며, 실지로 시스템을 개별소자로 구성하여 측정하였다.

• ETRI Journal
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• 제27권5호
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• pp.647-650
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• 2005

A new configuration to realize the most general n-th order voltage transfer function is proposed. It employs only one operational transresistance amplifier (OTRA) as the active element. In the synthesis of the transfer function, the RC:-RC decomposition technique is used. To the best of author's knowledge, this is the first topology to be used in the realization of n-th order transfer function employing single OTRA.

• 전력전자학회논문지
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• 제6권1호
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• pp.13-20
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• 2001

본 논문에서는 큰 출력 저항파 기준 전류와의 정합 특성이 우수한 새로운 전류 미러를 제안한다. CMOS 증폭기 회로에서 전원 전압이 작아지는 경우 출럭 전압의 스윙 폭이 전원 전압에 의해 제한되는 단점이 있으므로 제안된 회로는 이런 단점을 해결하기 위해 출력단의 스윙을 키우고, 안정된 동작올 할 수 있도록 한다. 출력단 부하가 큰 경우에 구동 능력을 증대시키고, 작은 전원 전압을 가질 때에도 큰 출력 스윙을 갖는 전류 미러를 시뮬레이션을 통해 가존의 캐스코드 전류 미러와 Regulated 전류 미러의 특성을 비교 및 고찰한다.

• 산업기술연구
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• 제11권
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• pp.43-53
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• 1991

Two kinds of simple active oscillators are proposed and analyzed assuming that operational amplifier has two-poles frequency characteristics. The first circuit is composed of one operational amplifier, one resistor and one grounded capacitor. The second oscillator is realized with one operational amplifier and three resitors. Proposed oscillators have the low sensitivity of the oscillation frequency for little variations of the passive element values. By the experimental results obtained with Op-Amp. ${\mu}A741$, the simple oscillators can be useful for the frequency range $1.25 KHz{\leq}f_{01}{\leq}40KHz$ for the active-RC type or $45.45 KHz{\leq}f_{02}{\leq}400KHz$ for the active-R oscillator, and it is shown to transform the active-R oscillator circuit into the voltage controlled type. Therefore, two kinds of oscillator circuit are attractive for the IC realization, because they have one operational amplifier, one resistor and one grounded capacitor, or three resistors.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2629-2632
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• 2003

This paper presents the harmonics rejection technique and the simulation of a active power filter using power operational amplifier. The proposed active power filter consists of CT(current transformer), harmonics detector and harmonics amplifier. The harmonics detector is a high pass filter using a GIC(Generalized Impedance Converter). The harmonics amplifier consists of a power operational amplifier and passive filters. The simulation has been implemented by OR-CAD program. It is examined whether the proposed active power filter can be realized or not through simple experiments.

• 전자공학회논문지B
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• 제32B권5호
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• pp.730-736
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• 1995

This paper presents the design of a CMOS programmable slew rate operational amplifier based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. By utilizing the newly designed circuit, it was proven that slew rate was linearly controlled and power dissipation was optimized. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience of timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 5. 83V/$\mu$s to 41.4V/$\mu$s, power dissipation ranging from 1.13mW to 4.1mW, and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.