• Title/Summary/Keyword: Operational Specifications

Search Result 92, Processing Time 0.024 seconds

Operational Assessment of Foodservice Information Systems in Hospital Foodservice Operations (병원 영양부서의 급식정보시스템 수행도 평가)

  • Choe, Seong-Gyeong;Kim, Jeong-Ri;Gwak, Dong-Gyeong
    • Journal of the Korean Dietetic Association
    • /
    • v.8 no.4
    • /
    • pp.387-397
    • /
    • 2002
  • Foodservice information systems management practices were assessed in hospital foodservice operations. A total of 46 dietetic departments were responded for the study and their practices of foodservice information systems were analyzed. The respondents were questioned about general characteristics of respondents as well as hospital foodservices implementation status of information systems. Statistical data analysis was completed using the SPSS package program for descriptive analysis, factor analysis, t-test and ANOVA test. 43.2% of total respondents gained informations by benchmarking of other hospital foodservice operations, but 7.8% gained through career education. They expected the enhanced efficiency of their tasks through implementing information systems. Based on factor analysis, information systems were divided into 6 management areas such as database management, meal management, nutrition management, purchasing management, production management and foodservice management. The average implementing scores were : database management 3.77, meal management 3.26, nutrition management 3.52, purchasing management 3.26, production management 2.73 and foodservice management 3.70 (score 1 indicates very poor and score 5 is very good). Among database management areas, standard recipe database and food item specifications database build-up scores(3.91) were relatively very high, but meal assessment and foodservice management reporting scores(2.43) were very low. The results suggest that it is necessary to build up automated foodservice management reporting system for the improvement of efficiency and productivity of operational tasks.

  • PDF

Design and Performance Prediction of Small Hydropower Plant Using Treated Effluent in Wastewater Treatment Plant (하수처리수를 이용한 소수력발전소 설계 및 성능예측)

  • Lee, Chul-Hyung;Park, Wan-Soon;Kim, Won-Kyoung;Kim, Jeong-Yeon;Chae, Kyu-Jung
    • Journal of the Korean Solar Energy Society
    • /
    • v.33 no.2
    • /
    • pp.78-83
    • /
    • 2013
  • A methodology to predict the output performance of small hydro power plant using treated effluent in waste water treatment plant has been studied. Existing waste water treatment plant located in Kyunggi-Do were selected and the output performance characteristics for these plants were analyzed. .Based on the models developed in this study, the hydrologic performance characteristics for SHP sites have been analyzed. The results show that the flow duration characteristics of small hydropower plant for waste water treatment plant have quite differences compared with small hydropower plant for the river. As a result, it was found that the developed model in this study can be used to analyze the output characteristics for small hydro power in waste water treatment plant. Additionally, primary design specifications such as design flowrate, capacity, operational rate and annual electricity production were estimated and discussed. It was found that the models developed in this study can be used to decide the design performance of small hydropower plant for waste water treatment plant effectively.

A Block Disassembly Technique using Vectorized Edges for Synthesizing Mask Layouts (마스크 레이아웃 합성을 위한 벡터화한 변을 사용한 블록 분할 기법)

  • Son, Yeong-Chan;Ju, Ri-A;Yu, Sang-Dae
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.38 no.12
    • /
    • pp.75-84
    • /
    • 2001
  • Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

  • PDF

Optimization of photovoltaic thermal (PV/T) hybrid collectors by genetic algorithm in Iran's residential areas

  • Ehyaei, M.A.;Farshin, Behzad
    • Advances in Energy Research
    • /
    • v.5 no.1
    • /
    • pp.31-55
    • /
    • 2017
  • In the present study, PV/T collector was modeled via analysis of governing equations and physics of the problem. Specifications of solar radiation were computed based on geographical characteristics of the location and the corresponding time. Temperature of the collector plate was calculated as a function of time using the energy equations and temperature behavior of the photovoltaic cell was incorporated in the model with the aid of curve fitting. Subsequently, operational range for reaching to maximal efficiency was studied using Genetic Algorithm (GA) technique. Optimization was performed by defining an objective function based on equivalent value of electrical and thermal energies. Optimal values for equipment components were determined. The optimal value of water flow rate was approximately 1 gallon per minute (gpm). The collector angle was around 50 degrees, respectively. By selecting the optimal values of parameters, efficiency of photovoltaic collector was improved about 17% at initial moments of collector operation. Efficiency increase was around 5% at steady condition. It was demonstrated that utilization of photovoltaic collector can improve efficiency of solar energy-based systems.

Nuclear Core Design for a Marine Small Power Reactor (선박용 소형동력로의 노심 핵설계)

  • 최유선;김종채;김명현
    • Journal of Energy Engineering
    • /
    • v.5 no.2
    • /
    • pp.146-152
    • /
    • 1996
  • A small power reactor core of 108 MW$\_$th/ was designed with some design constraints: 2 year refueling cycle length, soluble boron free operation, low power density, and proven fuel assembly design - Uljin 3'||'&'||'4 design specifications. CASMO-3 and KINS-3 was used to evaluate operational capability for power level control via control rods. Cycle length, power peaking factor, M.T.C., and power coefficients were also checked. Designed core loaded with KOFAs satisfied all design goals. We found that much more burnable poisons are to be loaded with axial enrichment zoning. Control rod assemblies should be located at every other assemblies with more than 3 banks. Additional shutdown banks are proposed for the safe plant cooldown, which could be located at core periphery.

  • PDF

Development of the Distributed Real-time Simulation System Based on HLA and DEVS (DEVS형식론을 적응한 HLA기반의 분산 실시간 시뮬레이션 시스템 개발)

  • Kim, Ho-Jeong;Lee, Jae-Hyun;Cho, Kil-Seok
    • Journal of the Korea Institute of Military Science and Technology
    • /
    • v.9 no.3
    • /
    • pp.25-32
    • /
    • 2006
  • Weapon systems composed of several subsystems execute various engagement missions in distributed combat environments in cooperation with a large number of subordinate/adjacent weapon systems as well as higher echelons through tactical data links. Such distributed weapon systems require distributed real-time simulation test beds to integrate and test their operational software, analyze their performance and effects of cooperated engagement, and validate their requirement specifications. These demands present significant challenges in terms of real-time constraints, time synchronization, complexity and development cost of an engagement simulation test bed, thus necessitate the use of high-performance distributed real-time simulation architectures, and modeling and simulation techniques. In this paper, in order to meet these demands, we presented a distributed real-time simulation system based on High Level Architecture(HLA) and Discrete Event System Specification(DEVS). We validated its performance by using it as a test bed for developing the Engagement Control System(ECS) of a surface-to-air missile system. The proposed technique can be employed to design a prototype or model of engagement-level distributed real-time simulation systems.

A Study on the Enterprise Architecture to Develop the Requirements for Railway Safety Support information Systems (철도안전정보 지원시스템의 요구사항 개발을 위한 엔터프라이즈 아키텍처 활용 연구)

  • Lee, Byoung-Gil;Lee, Jae-Chon
    • Journal of the Korean Society for Railway
    • /
    • v.10 no.6
    • /
    • pp.751-757
    • /
    • 2007
  • This paper is concerned with the development of the requirements for railway safety support information systems. The five safety elements at the system level have been modeled based on the enterprise architecture approach. Specifically, the modeling has been carried out as follows. First, the requirements are derived according to EIA-632 process. Also, the possible scenarios on the accident-investigation-support are developed from the help of relevant personnel in the area. The developed scenarios are reflected in modeling the operational and system architectures of DoDAF approach using a CASE tool. From this architecture model, we can easily get the specifications required for the operations. These results can give the improved understanding of the railway safety system to the members of diverse teams and areas working for the system development.

A Design Guide of 3-stage CMOS Operational Amplifier with Nested Gm-C Frequency Compensation

  • Lee, Jae-Seung;Bae, Jun-Hyun;Kim, Ho-Young;Um, Ji-Yong;Sim, Jae-Yoon;Park, Hong-June
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.7 no.1
    • /
    • pp.20-27
    • /
    • 2007
  • An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.

A Gm-C Filter using CMFF CMOS Inverter-type OTA (CMFF CMOS 인버터 타입 OTA를 이용한 Gm-C 필터 설계)

  • Choi, Moon-Ho;Kim, Yeong-Seuk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.23 no.4
    • /
    • pp.267-272
    • /
    • 2010
  • In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 ${\mu}m$ CMOS process; gm of 100 ${\mu}S$ and current of 100 ${\mu}A$ at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.

The Thermal Characterization of Chip Size Packages

  • Park, Sang-Wook;Kim, Sang-Ha;Hong, Joon-Ki;Kim, Deok-Hoon
    • Proceedings of the International Microelectronics And Packaging Society Conference
    • /
    • 2001.09a
    • /
    • pp.121-145
    • /
    • 2001
  • Chip Size Packages (CSP) are now widely used in high speed DRAM. The major driving farce of CSP development is its superior electrical performance than that of conventional package. However, the power dissipation of high speed DRAM like DDR or RAMBUS DRAM chip reaches up to near 2W. This fact makes the thermal management methods in DRAM package be more carefully considered. In this study, the thermal performances of 3 type CSPs named $\mu-BGA$^{TM}$$ $UltraCSP^{TM}$ and OmegaCSP$^{TM}$ were measured under the JEDEC specifications and their thermal characteristics were of a simulation model utilizing CFD and FEM code. The results show that there is a good agreement between the simulation and measurement within Max. 10% of $\circledM_{ja}$. And they show the wafer level CSPs have a superior thermal performance than that of $\mu-BGA.$ Especially the analysis results show that the thermal performance of wafer level CSPs are excellent fur modulo level in real operational mode without any heat sink.

  • PDF