• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10A
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• pp.922-929
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• 2005

This paper proposes an adaptive pilot beacon equipment for mobile communication systems based on direct spread spectrum technology which generates the pilot channel for handoff between base stations by using the information acquired from the downstream wireless signal regarding the overhead channel information. Such an adaptive pilot beacon equipment will enable low power operation since among the wireless signals, only the pilot channel will be generated and transmitted. The pilot channel in the downstream link of the CDMA receiver is used to acquire time and frequency synchronization and this is used to calibrate the offset for the beacon, which implies that time synchronization using GPS is not required and any location where forward receive signal can be received can be used as the installation site. The downstream link pilot signal searching within the CDMA receiver is performed by FPGA and DSP. The FPGA is used to perform the initial synchronization for the pilot searcher and DSP is used to perform the offset correction between beacon clock and base station clock. The CDMA transmitter the adaptive pilot beacon equipment will use the timing offset information in the pilot channel acquired from the CDMA receiver and generate the downstream link pilot signal synchronized to the base station. The intermediate frequency signal is passed through the FIR filter and subsequently upconverted and amplified before being radiated through the antenna.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1380-1386
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• 2009

In this paper, we propose a CQS(Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS(Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. Then, we simulated the area for each module and each memory. The area for each module is referenced by NAND($2{\times}1$) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). According to the increase of the memory’sentry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware.

• Korean Journal of Social Welfare
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• v.36
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• pp.101-127
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• 1998

The purpose of this study is to develop human resources and management system model for home-based welfare services. For the purpose of the study, both of method of literature review about home-based welfare services and previous research and survey were used in the study. The subjects of the survey were Junior and senior high school students, the employed, housewives, the disabled, and the aged. They were considered as human resources for the home-based welfare services. Based on the result of the survey and related theories, the study suggests the model for the development of volunteers and management system composed of recruitment, education and training, disposition, management and supervision, and evaluation for home-based welfare services. Assuming linking and cooperation between volunteer center and agency using volunteers which provide home-based welfare services, the model was developed. The role of volunteer center is recruitment, education and training. The agency using volunteers is responsible for education, disposition, supervision, and evaluation related to practice. In the stage of recruitment, elaborating strategy considering characteristics of group was suggested. In the campaign, use of mass media, selection of timing, equal opportunity for all group were suggested. Also outreach strategy as a effective recruitment strategy was presented. In the stage of education and training, method and content of education in each stage of primary education and re-education were presented. In the stage disposition, method and content for the right volunteer in the right place were suggested. In the stage of management and supervision, supervision by coordinator and necessity of using volunteers as para-professionals was suggested. Also the necessity of program operation for volunteer maintenance and management was discussed. In the stage of evaluation, time, main body, and method of evaluation was suggested.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.3 no.3
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• pp.19-26
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• 1983

Through traffic utilization of left turn lane constitutes an unique traffic operation at an intersection. Consequently, due to the provision as of current practice, conventional methods which estimate traffic volume and intersection capacity by lane would not be valid for design of signal timings. Through traffic utilization factor of left turn lane is affected by left turn volume and signal timings. The primary purpose of this study is to compare the results from leading left turn green phasing scheme with those from previously studied lagging left turn green phasing scheme in terms of utilization factor and intersection capacity by various left turn volume and signal timings, and thereby optimum signal timing to maximize the capacity at given left turn volume. Leading left turn green phasing increases capacity by 10~15 % as compared with that for current lagging left turn green phasing scheme. The range of optimum cycle length for left turn volume about 150 vph is 180~200 second. This cycle length range and left turn interval are longer than those for the lagging left turn green phasing scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.12 no.2
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• pp.63-75
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• 2013

Roundabouts have been operated in Europe, America and Australia since the 1970s, and many relevant researches continually was carried out. Though many studies regarding roundabout have been recently conducted in korea, most of them have focused on its operational safety and efficiency. Moreover, roundabout design guideline did not define a clear criteria related to pedestrian in roundabout, but seldom investigate the influences of pedestrian on crosswalk. In this study, we seek ways to operate the pedestrian crosswalk signal on roundabout maximizing their operational effects in exceptional case such as rush hour or intersection near the special facilities. We proved that roundabout signal operation is effective under certain circumstances in according to the number of pedestrian, and suggested the optimal signal timing plan for signalized roundabouts. For pursuing the above, we conducted the simulation test using the VISSIM model. The results show that the operational effectiveness of signalized roundabout was evaluated to be better than non-signalized roundabout in specific pedestrian volume condition. In addition, those results are confirmed using simulation analysis conducted on the real roundabout.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.2
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• pp.281-292
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• 2017

It is demanded to promote research and development of cyber weapons system and core technology in response to the ongoing cyber attack of North Korea. In this paper, core technologies of the future cyber weapon system are developed and the factors affecting the realization timing of core technologies were analyzed. 9 core technology groups and 36 core technologies are derived. Afterwards, these core technology groups are compared to the operation phase of the joint cyber warfare guideline and the cyber kill chain of Lockheed Martin. As a result of the comparison, it is confirmed that the core technology groups cover all phases of the aforementioned tactics. The results of regression analyses performed on the degree of influence by each factor regarding the moment of core technology realization show that the moment of core technology realization approaches more quickly as factors such as technology level of the most advanced country, technology level of South Korea, technology transfer possibility from the military sector to the non-military sector(spin-off factor), and technology transfer possibility from the non-military sector to the military sector(spin-on factor) increase. On the contrary, the moment of core technology realization is delayed as the degree at which the advanced countries keep their core technologies from transferring decrease. The results also confirm that the moment of core technology realization is not significantly correlated to the economic ripple effect factor. This study is meaningful in that it extract core technologies of cyber weapon system in accordance with revision of force development directive and join cyber warfare guideline, which incorporated cyber weapon system into formal weapon system. Furthermore, the study is significant because it indicates the influential factor of the moment of core technology realization.