• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.4
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• pp.998-1019
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• 2024

Mobile cloud computing is a very attractive service paradigm that outsources users' data computing and storage from mobile devices to cloud data centers. To protect data privacy, users often encrypt their data to ensure data sharing securely before data outsourcing. However, the bilinear and power operations involved in the encryption and decryption computation make it impossible for mobile devices with weak computational power and network transmission capability to correctly obtain decryption results. To this end, this paper proposes an outsourcing decryption algorithm of verifiable transformed ciphertext. First, the algorithm uses the key blinding technique to divide the user's private key into two parts, i.e., the authorization key and the decryption secret key. Then, the cloud data center performs the outsourcing decryption operation of the encrypted data to achieve partial decryption of the encrypted data after obtaining the authorization key and the user's outsourced decryption request. The verifiable random function is used to prevent the semi-trusted cloud data center from not performing the outsourcing decryption operation as required so that the verifiability of the outsourcing decryption is satisfied. Finally, the algorithm uses the authorization period to control the final decryption of the authorized user. Theoretical and experimental analyses show that the proposed algorithm reduces the computational overhead of ciphertext decryption while ensuring the verifiability of outsourcing decryption.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Journal of the Korea Institute of Military Science and Technology
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• v.18 no.2
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• pp.189-200
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• 2015

This paper gives an overview on the some potential applications and key technologies of biomimetic underwater robot for naval operations. Unlike most manned underwater naval systems, biomimetic underwater robots can be especially useful in near-land or harbour areas due to their ability to operate in shallow water effectively. Biomimetic underwater robot provide advantages in reaching locations that would be difficult or too dangerous for a manned vehicle to reach, as well as providing a level of autonomy that can remove the requirement for dedicated human operator support. Using multiple or schools of underwater robots would provide increased flexibility for navigation, communication and surveillance ability. And it alleviate some of the restrictions associated with speed and endurance design constraints.

• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.516-520
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• 2009

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyzed the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the RSA processor.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.3
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• pp.397-403
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• 2012

This paper describes a control method of turn-on/off angles to improve the efficiency of the switched reluctance generator(SRG) with a power closed-loop control system, and the inner-loop of the system is current hysteresis control. The SRG control system is constituted by the PI power controller and the two-level current hysteresis controller. By measuring and analyzing the system losses of different reference powers, speeds and turn-on/off angles, selection strategy of optimal turn-on/off angles is discussed. The proposed method is simple, reliable, and easy to achieve.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1562-1568
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• 2014

Based on the average method and the geometrical technique to calculate the average value, the average model of the open-loop step-up converter in CCM operation is established. The DC equilibrium point and corresponding small signal model is derived. The control-to-output transfer function is presented and analyzed. The theoretical analysis and PSIM simulations shows that the control-to-output transfer function includes not only the DC input voltage and the DC duty cycle, but also the two inductors, the two energy-transferring capacitors, the switching frequency and the load. Finally, the hardware circuit is designed, and the circuit experimental results are given to confirm the effectiveness of theoretical derivations and analysis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.5
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• pp.1693-1701
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• 2010

In this paper, requirements of efficient group key creation in multiple hierarchy structure environment with clear distinction of hierarchical roles within organizations are explained and the method of creating a group key that satisfies such requirements is proposed. The proposed method creates the group key through logical sum operation of hierarchy identifier created using uni-directional hash chain and group identifier randomly created according to the access right. The problem of excessive possession of key information by upper group users in the existing static group key creation technique was resolved. At the same time, lower group users were prevented from deducing key information of upper group users. In addition, as a result of comparative analysis performed with an experiment on existing super group key creation technique and multiple hierarchy group key method, the proposed method was found to be equivalent or superior to existing method in terms of various items including the total number of keys created, the number of keys possessed by users, the number of keys used for encoding and decoding of information, and expandability of keys.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1470-1478
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• 2018

Recently, wireless power transfer (WPT) via coupled magnetic resonances has attracted a lot of attention owing to its long operation distance and high efficiency. However, the WPT systems is over-coupling and a frequency splitting phenomenon occurs when resonators are placed closely, which leads to a decrease in the transfer power. To solve this problem, an adaptive frequency tracking control (AFTC) was used based on a closed-loop control scheme. An improved particle swarm optimization (PSO) algorithm was proposed with the AFTC to track the maximum power point in real time. In addition, simulations were carried out. Finally, a WPT system with the AFTC was demonstrated to experimentally validate the improved PSO algorithm and its tracking performance in terms of optimal frequency.

• Convergence Security Journal
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• v.10 no.3
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• pp.29-41
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• 2010

Survelliance and Reconnaissance Sensor Network(SRSN) which can collect various tactical information within battlefield in real time plays an important role in NCW environment, of sensor to shooter architecture. However, due to the resource-limited characteristics of sensor nodes and the intrinsic attributes of sensor network such as wireless communication, the SRSN may be vulnerable to various attacks compared to traditional networks. Therefore, in this paper, we propose a new group key management scheme to guarantee confidentiality, integrity, availability, and authentication during the operation of the SRSN. Proposed scheme generates and distributes the group key based on the topological characteristic of the SRSN and the probabilistic key sharing. The communication cost for distributing the group key is O(logn).