• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.49-57
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• 2002

In this paper, we deal with a real time implementation of the integrated image-based navigation parameter extraction system using the TMS320C80 MVP(multimedia video processor). Our system consists of relative position estimation and absolute position compensation, which is further divided into high-resolution aerial image matching, DEM(Digital elevation model) matching, and IRS (Indian remote sensing) satellite image matching. Those algorithms are implemented in real time using the MVP. To achieve a real-time operation, an attempt is made to partition the aerial image and process the partitioned images in parallel using the four parallel processors in the MVP. We also examine the performance of the implemented integrated system in terms of the estimation accuracy, confirming a proper operation of the our system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.176-184
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• 2005

In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.266-271
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• 1999

The purpose in this study has to development the system on increasing operation of old-typed transceiver for solve the question that limited allocation frequencies and continuesly icreasment of traffic. Therefore, we are desigened the remote control system that has the function for variable channels, PTT and monitoring of transmission power and frequencies. Exchange of control data is to hold in common the twist two-wire or telephone line for the voice transmission. The H/W is consist of FSK and MCS-51 processor which are up-down control of channel, n control and monitoring display by serial data transmission. According to the simplex traffic operation is designed the algorithm of serial data transmission by sequential transmission sequence and protocol. The S/W of sequential transmission sequence is designed to usefully the intergrated communications system which is able to connection between the multi-transceiver and multi-terminal by master processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.473-480
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• 2009

This paper is to enhance a color image running in the PXA255 ARM processor based on embedded linux environments. Retinex is one of the representative algorithm for image enhancement in the previous research. However, retinex is not suitable the run on the embedded system because of its long processing time. So, we proposed the image enhancement algorithm for embedded system, with less quantity of operation and the effect equivalent to retinex. To achieve this goal, we propose and implement the image enhancement algorithm, which utilizes the image formation model and gamma correction to be effective in a back-light and dark image. The proposed algorithm converts the color space from RGB to HSV, and then V and S channels are processed. In order to optimize the proposed method in the PXA255 ARM processor, quantity of calculation is reduced. The performance of the proposed algorithm was evaluated through qualitative method and quantitative method. The results show that brightness and contrast are improved with less quantity of operation.

• Journal of Hydrogen and New Energy
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• v.17 no.3
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• pp.293-300
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• 2006

KIER has been developing a Ru-based preferential oxidation catalysts and a novel fuel processing system to provide hydrogen rich gas to residential PEMFCs system. The catalytic activity of Ru-based catalysts was investigated at different Ru loading amount and different support structure. The obtained result indicated that 2 wt% loaded Ru-based catalyst supported on ${\alpha}-Al_2O_3$ showed high activity in low temperature range and suppressed the methanation reaction. The developed prototype fuel processor showed thermal efficiency of 78% as a HHV basis with methane conversion of 92%. CO concentration below 10 ppm in the produced gas is achieved with separate preferential oxidation unit under the condition of $[O_2]/[CO]=2.0$. The partial load operation have been carried out to test the performance of fuel processor from 40% to 80% load, showing stable methane conversion and CO concentration below 10 ppm. The durability test for the daily start-stop and 8 h operation procedure is under investigation and shows no deterioration of its performance after 50 start-stop cycles. In addition to the system design and development.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.8-15
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• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.1-12
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• 1999

In this paper, we designed an embedded processor with 128Kbytes EPROM and 4Kbytes SRAM based on GMS30C2132 which RISC processor with DSP functions. And a new architecture of bus sharing to control the embedded memory and external memory unit i proposed aiming at one-cycle access between memories and CPU. For embedded 128Kbytes EPROM, we designed the new expansion interface for data size at data ordering with memory organization and the efficient interface for test. The embedded SRAM supports an extended stack area high speed DSP operation, instruction cache and variable data-length control which is accessed with 4K modulo addressing schemes. The proposed new architecture and circuits reduced the memory access cycle time from 40ns and improved operation speed 2-times for program benchmark test. The chip is occupied $108.68mm^2$ using $0.6{\mu}m$ CMOS technology.

• Journal of Korea Society of Digital Industry and Information Management
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• v.13 no.2
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• pp.13-25
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• 2017

Recently, the high performance of tactical situation display console and tactical data links are used to integrate the operational situations in accordance with information age and NCW (Network Centric Warfare). The tendency to maximize the efficiency of task execution has been developed by sharing information and the state of the battle quickly through complex and diverse information exchange. Tactical data link is a communication system that shares the platform with core components of weapons systems and battlefield situation between the command and control systems to perform a Network Centric Warfare and provides a wide range of tactical data required for decision-making and implementation.It provides the tactical information such as tactical information such as operational information, the identification of the peer, and the target location in real time or near real time in the battlefield situation, and it is operated for the exchange of mass tactical information between the intellectuals by providing common situation recognition and cooperation with joint operations. In this study, still image management, audio file management, tactical screen recording and playback using the storage and playback, NITF (National Imagery Transmission Format) message received from the displayer integrates the tactical situation in three dimensions according to multiple data link operation to suggest ways to ensure data integrity between the data link processor during the entire operation time.