• Journal of IKEEE
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• v.27 no.4
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• pp.683-686
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• 2023

In this paper, we designed a Delayed Dual Core Lock-Step (D-DCLS) processor where two cores operate same instructions with delay and the result is compared to mitigate soft errors and common mode failures in automotive electronic systems. Because D-DCLS does not know which core an error occurred in, each core must be recovered to the point before the error occurred, but complex hardware modifications are required to return all intermediate values on the pipeline stage. In this paper, in order for easy hardware implementation, all register values are saved to a buffer whenever a branch instruction is executed. When an error is detected, the saved register values are automatically restored, and then 'BX LR' instruction is executed to return to the last branch point. The proposed D-DCLS processor was designed using Verilog HDL and was confirmed to continue normal operation after automatically recovering error.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.2
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• pp.145-150
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• 1999

A real-time control system, composed of the controlled processor and the controller computer(s), may have a variety of task types, some of which have tight timing-constraints in generating the correct control input. The maximum period of those task failures tolerable by the system is called the hard deadline, which depends on not only fault characteristics but also task characteristics. In the paper, we extend a method deriving the hard deadline in LTI system executing single task. An algorithm to combine the deadlines of all the elementary tasks in the same operation-mode is proposed to derive the hard deadline of the entire system. For the end, we modify the state equation for the task to capture the effects of task failures (delays in producing correct values) and inter-correlation. We also classify the type of executing the tasks according to operation modes associated with relative importance of correlated levels among tasks, into series, parallel, and cascade modes. Some examples are presented to demonstrate the effectiveness of the proposed methods.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.5
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• pp.433-438
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• 2012

In this paper, a operation network system equipped with onboard wireless communication systems and ground-based mission control systems is proposed for swarm flight of small UAVs. This operating system can be divided into two networks, UAV communication network and ground control system. The UAV communication network is intend to exchange the informations of navigation, mission and flight status with minimum time delay. The ground control system consisted of mission control systems and UDP network. Proposed operation network system can make a swarm flight of various UAVs, execute complex missions decentralizing mission to several UAVs and cooperte several missions. Finally, PILS environments are developed based on the total operating system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.89-99
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• 1995

One of the hardest problems that limit real application of production system is its slowness. One way to overcome this problem is to speed up the matching operation which occupies more than 90% of the total execution time. In this paper, we try to speed up the matching operation with parallel execution of a typical pattern matching algorithm, RETE, in a multiprocessor environment, This requires not only to make partitions of the rules but also to allocate the partitioned rules to processors, respectively. A partition strategy is proposed to make groups of similar rules by evaluating the similarity of rules according to the number of common conditions between rules. An allocation strategy is proposed to make the load of each processor even by assigning the different priority to the group of rules according to the expected amount of time required for matching operation. To compare with the existing methods, we perform simulation using OPS5 sample programs. The simulation results show that the proposed methods can improve the performance of production system.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.291-291
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• 2000

A vehicle driving simulator is a virtual reality device which a human being feels as if the one drives a vehicle actually. Driving Operation System acts as an interface between a driver and a driving simulator. This paper suggests the driving operation system for a driving simulator. This system consists of a controller, DC geared motor, MR brake, rotary encoders, steeping motor and bevel gear box. Reaction force and torque on the steering system were made by DC_Motor and MR_Brake. Reaction force and torque on the steering system were compare between real car and a driving simulator. The controller based on the 80C196KC micro processor that manage and transfer signal.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.677-681
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• 2005

This Paper presents a 6 pulse shift operation control mode of current-source-inverter to make improvement of efficiency and to reduce the frequency of inverter switching for photovoltaic generation system using PWM current-source-inverter. This system is connected solar cell energy directly without using a storage cell. The proposed circuit can maintain maximum voltage of photovoltaic generation of take advantage of six Buck-Boost converter and a full-bridge inverter determines the polarity of AC output. That is controlled by using digital signal processor TMS320F2812 for operation about a 6 pulse shift operation control of current-source-inverter, and it is verified through the experimental results.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.4
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• pp.272-281
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• 2000

This paper deals with the parallel operation of several numbers of PWM converters for a high speed railway train application. Several considerations are made to reduce the transformer interaction which can cause a current control problem in severe case. Also, in this paper, novel control strategy is proposed to achieve a harmonic free primary-side current control under a light load condition using one current sensor independent of the number of converters. In addition, the modified predictive current controller, which is suitable to a digital current controller with a relatively large sampling period, is used. Finally, to verify the system validity, digital control system with TMS320C44 micro-processor and small scale simulator are made and tested.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.48-58
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• 2006

This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• Journal of Information Processing Systems
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• v.16 no.6
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• pp.1359-1371
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• 2020

In transmitting and receiving such a large amount of data, reliable data communication is crucial for normal operation of a device and to prevent abnormal operations caused by errors. Therefore, in this paper, it is assumed that an error correction code (ECC) that can detect and correct errors by itself is used in an environment where massive data is sequentially received. Because an embedded system has limited resources, such as a low-performance processor or a small memory, it requires efficient operation of applications. In this paper, we propose using an accelerated ECC-decoding technique with a graphics processing unit (GPU) built into the embedded system when receiving a large amount of data. In the matrix-vector multiplication that forms the Hamming code used as a function of the ECC operation, the matrix is expressed in compressed sparse row (CSR) format, and a sparse matrix-vector product is used. The multiplication operation is performed in the kernel of the GPU, and we also accelerate the Hamming code computation so that the ECC operation can be performed in parallel. The proposed technique is implemented with CUDA on a GPU-embedded target board, NVIDIA Jetson TX2, and compared with execution time of the CPU.