• Journal of the Korean Society for Precision Engineering
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• v.21 no.8
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• pp.143-151
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• 2004

This paper deals with the precision NURBS interpolator for wire-EDM. Previous research about OAC (Open Architecture Controller) is mostly aimed at NC cutting machines such as milling or lathes, and hence these results are inadequate to apply to wire-EDM. In contradiction to NC machines, wire-EDM operates relatively slow feed rates and based on a feedback control loop to the machining process. The 2-stage interpolation method which reflects wire-EDM specific characteristics was proposed. The constant interpolation error could be acquired through 1 st stage interpolation. Feed rate regulation was performed through 2nd stage interpolation. The suggested algorithm was implemented to test-bed PC-NC system. Computer simulations and the experimental machining were conducted.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.2
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• pp.49-56
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• 2008

This paper proposes a PC-based open architecture controller for a multi-axis robotic manipulator. The designed controller can be applied for various multi-axes robotic manipulators since the motion controller is implemented on a PC with its peripheral devices. The accuracy of the controller based on the computed torque method has been measured with the dynamic model of manipulator. Since the controller is implemented in the PC-based architecture, it is free from the user circumstances and the operating environment. Dynamics of the manipulator have been compensated by the feed forward path in the inner loop and the resulting linear outer loop has been controlled by PD algorithm. Using the specialized language, it can be more efficient in programming and in driving of the multi-axis robot. Unlike the conventional controller that is used to control only a specific robot, this controller can be easily changed for various types of robots. This paper proposes a PC-based controller that has a simple architecture with its simple interface circuits than general commercial controllers. The maintenance and the performance of the controller can be easily improved for a specific robot. In fact, using a Samsung multi-axis robot, AT1, the controller performance and convenience of the PC-based controller have been verified by comparing to the commercial one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5C
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• pp.534-539
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• 2006

In this paper, we propose a new frame prediction filtering technique and a hardware(H/W) architecture for scalable video coding. We try to evaluate MCTF(motion compensated temporal filtering) and hierarchical B-picture which are a technique for eliminate correlation between video frames. Since the techniques correspond to non-causal system in time, these have fundamental defects which are long latency time and large size of frame buffer. We propose a new architecture to be efficiently implemented by reconfiguring non-causal system to causal system. We use the property of a repetitive arithmetic and propose a new frame prediction filtering cell(FPFC). By expanding FPFC we reconfigure the whole arithmetic architecture. After the operational sequence of arithmetic is analyzed in detail and the causality is imposed to implement in hardware, the unit cell is optimized. A new FPFC kernel was organized as simple as possible by repeatedly arranging the unit cells and a FPFC processor is realized for scalable video coding.

• International Journal of Naval Architecture and Ocean Engineering
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• v.7 no.2
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• pp.346-363
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• 2015

We have performed integrated dynamics modeling for a supercavitating vehicle. A 6-DOF equation of motion was constructed by defining the forces and moments acting on the supercavitating body surface that contacted water. The wetted area was obtained by calculating the cavity size and axis. Cavity dynamics were determined to obtain the cavity profile for calculating the wetted area. Subsequently, the forces and moments acting on each wetted part-the cavitator, fins, and vehicle body-were obtained by physical modeling. The planing force-the interaction force between the vehicle transom and cavity wall-was calculated using the apparent mass of the immersed vehicle transom. We integrated each model and constructed an equation of motion for the supercavitating system. We performed numerical simulations using the integrated dynamics model to analyze the characteristics of the supercavitating system and validate the modeling completeness. Our research enables the design of high-quality controllers and optimal supercavitating systems.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 1995.11a
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• pp.153-165
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• 1995

When an automatic course-keeping is introduced as is quite popular in modern navigation the closed-loop steering system consists of autopilot device power unit(or telemotor unit) steering gear ship dynamics and magnetic or gyro compass. We derive the mathematical model of each element of the automatic steering system. We provide a method of theoretical analysis on propulsive energy loss related to automatic steering of ships inthe open seas taking account of the on-off mechanism of power unit. Also we paid attention to dead band mechanism of autopilot device which is normally called weather adjustment. Next we make numerical calculation of the effects of autopilot control constants ont he propulsive energy loss for two kinds of ship a fishing boat and an ore carrier. Realistic sea and wind disturbances are employed in the calculation.

• Wind and Structures
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• v.11 no.5
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• pp.345-359
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• 2008

An experimental investigation of the flow over the rectangular body located in close proximity to a ground board was reported using the particle image velocimetry (PIV) technique. The present experiments were conducted in a closed-loop open surface water channel with the Reynolds number, $Re_H=1.2{\times}10^4$ based on the model height. In addition to the PIV measurements, flow visualization studies were also carried out. The PIV technique provided instantaneous and time-averaged velocity vectors map, vorticity contours, streamline topology and turbulent quantities at various locations in the near wake. In the vertical symmetry plane, the upperbody flow is separated from the sharp top leading edge of the model and formed a large reverse flow region on the upper surface of the model. The flow structure downstream of the model has asymmetric double vortices. In the horizontal symmetry plane, identical separated flow regions occur on both vertical side walls and a pair of primary recirculatory bubbles dominates the wake region.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.391-406
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• 2014

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.11
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• pp.1117-1123
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• 2008

This paper implements dual-kernel system using standard Linux and real-time embedded Linux for the real-time control of intelligent robot systems. Such system provides more useful services including standard Linux thread that is easy to implement complicated tasks and real-time tasks for the deterministic response to velocity control. Here, an open source real-time embedded Linux, XENOMAI, is ported on embedded target board. And for interfacing with motor controller we adopted a real-time serial device driver. The real-time task was implemented with a priority to keep the cyclic control command for trajectory control. In order to validate deterministic response of the proposed system, the performance measurement of the delay in performing trajectory control with feedback loop is evaluated with non real-time standard Linux. The proposed software architecture is anticipated to take advantage of features in both standard Linux and real-time operating systems for the intelligent robot systems.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.955-958
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• 2003

본 논문에서는 개방형 파이프라인 구조를 이용한 8비트 500Msamples/s ADC를 제안하였다. 8-비트의 해상도에 적합하면서 전력 소모가 적은 5 단 파이프라인 구조로 설계하였으며, 고속 동작에 적합하게 MUX 스위치에서 선택한 신호를 인터폴레이션하는 개방형 구조를 채택하였다. 전력 소모와 전체 칩 면적을 줄이기 위해서, 각 단에서 필요한 신호의 수를 줄이도록 설계하였다. 설계된 ADC 는 3 개의 신호를 이용하여 구현 함으로서 각 단에서의 증폭기 수틀 줄일 수 있었다. 또한 1.8V 의 낮은 전원 전압에 의한 작은 입력 범위에서 8-비트의 해상도를 만족하기 위해서 Offset Cancellation 기법을 사용하였다. 제안된 ADC 는 0.18μ m 일반 CMOS 공정을 이용하여 설계되었으며 시뮬레이션 결과 500Msamples/s에서 220mW의 전력 소모를 가지며, 1.2Vp-p (Differential) 입력 범위에 대해서 약 48dB의 SNDR을(8-비트의 해상도) 가짐을 확인할 수 있었다.