• Title/Summary/Keyword: On-off current ratio

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Identification of In-Home Appliance Types Based on Analysis of Current Consumption Using Energy Metering Circuit

  • Tran, Tin Trung;Pham, Trung Xuan;Kim, Jong-Wook
    • IEMEK Journal of Embedded Systems and Applications
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    • v.12 no.2
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    • pp.79-88
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    • 2017
  • One of the important applications of activity sensing in the home is energy monitoring. Many previous methodologies for detecting and recognizing household appliances have been proposed. This paper presents an approach that uses an energy metering circuit (EMC) to classify and identify the various electrical devices in home based on root-mean-square (RMS) consumed current value. EMC gathers the RMS current values created by appliance state transition (e.g., on to off) and apparatus operating process. In this paper, an identification algorithm is proposed to detect a change in current levels using the standard deviation of current signals and their average values. In addition, characteristic of the appliance is extracted concerning four feature parameters concerning the number of current levels, the minimum level, the maximum level, and signal-to-noise ratio (SNR) of them. Experiment results validate the reliable performance of the proposed identification method for 11 representative appliances.

Effects of multi-stacked hybrid encapsulation layers on the electrical characteristics of flexible organic field effect transistors

  • Seol, Yeong-Guk;Heo, Uk;Park, Ji-Su;Lee, Nae-Eung
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.257-257
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    • 2010
  • One of the critical issues for applications of flexible organic thin film transistors (OTFTs) for flexible electronic systems is the electrical stabilities of the OTFT devices, including variation of the current on/off ratio ($I_{on}/I_{off}$), leakage current, threshold voltage, and hysteresis, under repetitive mechanical deformation. In particular, repetitive mechanical deformation accelerates the degradation of device performance at the ambient environment. In this work, electrical stabilities of the pentacene organic thin film transistors (OTFTs) employing multi-stack hybrid encapsulation layers were investigated under mechanical cyclic bending. Flexible bottom-gated pentacene-based OTFTs fabricated on flexible polyimide substrate with poly-4-vinyl phenol (PVP) dielectric as a gate dielectric were encapsulated by the plasma-deposited organic layer and atomic layer deposited inorganic layer. For cyclic bending experiment of flexible OTFTs, the devices were cyclically bent up to $10^5$ times with 5mm bending radius. In the most of the devices after $10^5$ times of bending cycles, the off-current of the OTFT with no encapsulation layers was quickly increased due to increases in the conductivity of the pentacene caused by doping effects from $O_2$ and $H_2O$ in the atmosphere, which leads to decrease in the $I_{on}/I_{off}$ and increase in the hysteresis. With encapsulation layers, however, the electrical stabilities of the OTFTs were improved significantly. In particular, the OTFTs with multi-stack hybrid encapsulation layer showed the best electrical stabilities up to the bending cycles of $10^5$ times compared to the devices with single organic encapsulation layer. Changes in electrical properties of cyclically bent OTFTs with encapsulation layers will be discussed in detail.

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A Researching about Reducing Leakage Current of Polycrystalline Silicon Thin Film Transistors with Bird's Beak Structure (누설전류 감소를 위한 Bird's Beak 공정을 이용한 다결정 실리콘 박막 트랜지스터의 구조 연구)

  • Lee, Jin-Min
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.2
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    • pp.112-115
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    • 2011
  • To stabilize the electric characteristic of Silicon Thin Film Transistor, reducing the current leakage is most important issue. To reduce the current leakage, many ideas were suggested. But the increase of mask layer also increased the cost. On this research Bird's Beak process was use to present element. Using Silvaco simulator, it was proven that it was able to reduce current leakage without mask layer. As a result, it was possible to suggest the structure that can reduce the current leakage to 1.39nA without having mask layer increase. Also, I was able to lead the result that electric characteristic (on/off current ratio) was improved compare from conventional structure.

New Graphene Electronic Device Structure for High Ion/Ioff Ratio

  • Jeong, Hyeon-Jong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.08a
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    • pp.112-112
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    • 2012
  • Graphene has been considered as one of the potential post Si-materials due to its high mobility. [1] However, since graphene is semi-conductor with zero band gap, it is difficult to achieve high Ion/Ioff ratio, one of the most important requirements for commercial devices. There have been many attempts to open its band gap for high Ion/Ioff ratio, but most of them end up lowering the mobility. [2-5] Thus, we proposed and demonstrated a new device structure for graphene transistor based on one of the unique properties of graphene for high Ion/Ioff: using this approach, we were able to achieve the ratio over $10^5$. [6] Our device has several major advantages over previously proposed graphene based electronic devices. Since our device does not alter the given properties of graphene, such as opening the band gap, it has no fundamental issues on mobility degradations. In addition, our device is fully compatible with current Si technology and we were able to fabricate the devices with 6 inch wafer scale with CVD (Chemical Vapor Deposition) grown graphene. In this presentation, we will discuss about the details of our graphene device including the device structure and the detailed understanding of working mechanism. We will present device characteristics including I-V curves with $10^5$ on/off ratio. We will also present the performance of an inverter based on our devices. Finally, we will discuss the current issues and their potential solutions.

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Two Branches of Tsushima Warm Current in the Western Channel of the Korea Strait (韓國海峽 西水道에서 對馬暖流의 2個 支流)

  • Byun, Sang-Kyung;Chang, Sun-Duck
    • 한국해양학회지
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    • v.19 no.2
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    • pp.200-209
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    • 1984
  • On the basis of oceanographic observation conducted in summer 1982, the flow pattern of the Tsushima Warm Current definitely showed two branches with high surface velocity more than 70 cm/sec in the western channel of Korea Strait. One of the branches, the East Korea Warm Current, found about 8 km off Pusan flows northward along the east coast of Korea and the other branch, located at about 20km off Pusan flows east after passing the Korea Strait. The branching of two flows already occurred before the Tsushima Warm Current reaches the Pusan Tsushima section, and the volume transport and the widths of the two branches are not much different from each other. The number of branches may be controlled by the width of western channel and the flow of two branches may also be related to the variation of layer depth and the widening ratio of widths between the western channel and the Japan Sea (East Sea).

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Ultra-Low Powered CNT Synaptic Transistor Utilizing Double PI:PCBM Dielectric Layers (더블 PI:PCBM 유전체 층 기반의 초 저전력 CNT 시냅틱 트랜지스터)

  • Kim, Yonghun;Cho, Byungjin
    • Korean Journal of Materials Research
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    • v.27 no.11
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    • pp.590-596
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    • 2017
  • We demonstrated a CNT synaptic transistor by integrating 6,6-phenyl-C61 butyric acid methyl ester(PCBM) molecules as charge storage molecules in a polyimide(PI) dielectric layer with carbon nanotubes(CNTs) for the transistor channel. Specifically, we fabricated and compared three different kinds of CNT-based synaptic transistors: a control device with $Al_2O_3/PI$, a single PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%), and a double PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%)/PI:PCBM(0.05 wt%). Statistically, essential device parameters such as Off and On currents, On/Off ratio, device yield, and long-term retention stability for the three kinds of transistor devices were extracted and compared. Notably, the double PCBM device exhibited the most excellent memory transistor behavior. Pulse response properties with postsynaptic dynamic current were also evaluated. Among all of the testing devices, double PCBM device consumed such low power for stand-by and its peak current ratio was so large that the postsynaptic current was also reliably and repeatedly generated. Postsynaptic hole currents through the CNT channel can be generated by electrons trapped in the PCBM molecules and last for a relatively short time(~ hundreds of msec). Under one certain testing configuration, the electrons trapped in the PCBM can also be preserved in a nonvolatile manner for a long-term period. Its integrated platform with extremely low stand-by power should pave a promising road toward next-generation neuromorphic systems, which would emulate the brain power of 20 W.

An Application of Data Mining Techniques in Electronic Commerce (전자상거래에서 지식탐사기법의 활용에 관한 연구)

  • Sung Tae-Kyung;Chu Seok-Chin;Kim Joong-Han;Hong Jun-Seok
    • The Journal of Information Systems
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    • v.14 no.2
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    • pp.277-292
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    • 2005
  • This paper uses a data mining approach to develop bankruptcy prediction models suitable for traditional (off-line) companies and electronic (on-line) companies. It observes the differences in the composition prediction models between these two types of companies and provides interpretation of bankruptcy classifications. The bankruptcy prediction models revealed the major variables in predicting bankruptcy to be 'cash flow to total assets' and 'gross value-added to net sales' for traditional off-line companies while 'cash flow to liabilities','gross value-added to net sales', and 'current ratio' for electronic companies. The accuracy rates of final prediction models for traditional off-line and electronic companies were found to be $84.7\%\;and\;82.4\%$, respectively. When the model for traditional off-line companies was applied for electronic companies, prediction accuracy dropped significantly in the case of bankruptcy classification (from $70.4\%\;to\;45.2\%$) at the level of a blind guess ($41.30\%$). Therefore, the need for different models for traditional off-line and electronic companies is justified.

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A Study on Low Temperature Sequential Lateral Solidification(SLS) Poly-Si Thin Film Transistors(TFT′s) with Molybdenum Gate (Molybdenum 게이트를 적용한 저온 SLS 다결정 TFT′s 소자 제작과 특성분석에 관한 연구)

  • 고영운;박정호;김동환;박원규
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.6
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    • pp.235-240
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    • 2003
  • In this paper, we present the fabrication and the characteristic analysis of sequential lateral solidification(SLS) poly-Si thin film transistors(TFT's) with molybdenum gate for active matrix liquid displays (AMLCD's) pixel controlling devices. The molybdenum gate is applied for the purpose of low temperature processing. The maximum processing temperature is 55$0^{\circ}C$ at the dopant thermal annealing step. The SLS processed poly-Si film which is reduced grain and grain boundary effect, is applied for the purpose of electrical characteristics improvements of poly-Si TFT's. The fabricated low temperature SLS poly-Si TFT's had a varying the channel length and width from 10${\mu}{\textrm}{m}$ to 2${\mu}{\textrm}{m}$. And to analyze these devices, extract electrical characteristic parameters (field effect mobility, threshold voltage, subthreshold slope, on off current etc) from current-voltage transfer characteristics curve. The extract electrical characteristic of fabricated low temperature SLS poly-Si TFT's showed the mobility of 100~400cm$^2$/Vs, the off current of about 100pA, and the on/off current ratio of about $10^7$. Also, we observed that the change of grain boundary according to varying channel length is dominant for the change of electrical characteristics more than the change of grain boundary according to varying channel width. Hereby, we comprehend well the characteristics of SLS processed poly-Si TFT's witch is recrystallized to channel length direction.

Temperature dependent hysteresis characteristics of a-Si:H TFT (비정질 실리콘 박막 트랜지스터 히스테리시스 특성의 온도의존성)

  • 이우선;오금곤;장의구
    • Electrical & Electronic Materials
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    • v.9 no.3
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    • pp.277-283
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    • 1996
  • The temperature dependent characteristics of hydrogenerated amorphous silcon thin film transistor (a-Si:H TFT) with a bottom gate of N-Type <100> Si wafer were investigated. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the gate voltage increased and decreased with the small gate voltage. According to the variation of gate voltages, drain current of TFT increased by temperature increase, and hysteresis characteristics mainly depended on the temperature increase. The hysteresis current showed negative characteristics curve over 383K. The hysteresis occurance area and the differences of forward and reverse sweep were increased at the higher temperature. Hysteresis current of I$_{d}$(on/off) ratio decreased at the lower temperature and increased at the higher temperature.e.

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Formation of PVP- Based Organic Insulating Layers and Fabrication of OTFTs (PVP-기반 유기 절연막 형성과 OTFT 제작)

  • Jang, Ji-Geun;Seo, Dong-Gyoon;Lim, Yong-Gyu
    • Korean Journal of Materials Research
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    • v.16 no.5
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    • pp.302-307
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    • 2006
  • The formation and processing of organic insulators on the device performance have been studied in the fabrication of organic thin film transistors (OTFTs). The series of polyvinyls, poly-4-vinyl phenol(PVP) and polyvinyltoluene (PVT), were used as solutes and propylene glycol monomethyl ether acetate(PGMEA) as a solvent in the formation of organic insulators. The cross-linking of organic insulators was also attempted by adding the thermosetting material, poly (melamine-co-formaldehyde) as a hardener in the compound. The electrical characteristics measured in the metal-insulator-metal (MIM) structures showed that insulating properties of PVP layers were generally superior to those of PVT layers. Among the layers of PVP series: PVP(10 wt%) copolymer, 5 wt% cross-linked PVP(10 wt%), PVP(20 wt%) copolymer, 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%), the 10 wt% cross-linked PVP(20 wt%) layer showed the lowest leakage current characteristics. Finally, inverted staggered OTFTs using the PVP(20 wt%) copolymer, 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%) as gate insulators were fabricated on the polyether sulphone (PES) substrates. In our experiments, we could obtain the maximum field effect mobility of 0.31 $cm^2/Vs$ in the device from 5 wt% cross-linked PVP(20 wt%) and the highest on/off current ratio of $1.92{\times}10^5$ in the device from 10 wt% cross-linked PVP(20 wt%).