• Journal of the Semiconductor & Display Technology
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• v.17 no.1
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• pp.62-65
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• 2018

In the era of the 4th Industrial Revolution, IoT products of various and specialized fields are being developed and produced. Especially, the generation of the artificial intelligence, robotic technology Multilayer substrates and packaging technologies in the notebook, mobile device, display and semiconductor component industries are demanding the need for flexible materials along with miniaturization and thinning. To do this, this work use FCCL (Flexible Copper Clad Laminate), which is a flexible printed circuit board (PCB), to implement FPCB (Flexible PCB), COF (Chip on Film) Use is known to be essential. In this paper, I propose a transfer device which prevents the occurrence of scratches by analyzing the mechanism of wrinkle and scratch mechanism during the transfer process of thin film material in which the thickness increases while continuously moving in air or solution.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.124-130
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• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.33-38
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• 2001

We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.33-38
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• 2007

We studied a bonding at low temperature using polymer bump and Non-Conductive Adhesive (NCA), and studied the reliability of the polymer bump/Al pad joints. The polymer bumps were formed on oxidized Si substrates by photolithography process, and the thin film metals were formed on the polymer bumps using DC magnetron sputtering. The substrate used was AL metallized glass. The polymer bump and Al metallized glass substrates were joined together at $80^{\circ}C$ under various pressure. Two NCAs were applied during joining. Thermal cycling test ($0^{\circ}C-55^{\circ}C$, cycle/30 min) was carried out up to 2000 cycles to evaluate the reliability of the joints. The bondability was evaluated by measuring the contact resistance of the joints through the four point probe method, and the joints were observed by Scanning Electron Microscope (SEM). The contact resistance of the joints was $70-90m{\Omega}$ before the reliability test. The joints of the polymer bump/Al pad were damaged by NCA filler particles under pressure above 200 MPa. After reliability test, some joints were electrically failed since thinner metal layers deposited at the edge of bumps were disconnected.

• Journal of electromagnetic engineering and science
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• v.6 no.2
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• pp.135-145
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• 2006

This paper presents the theory, design, fabrication and characterization of the novel low actuation voltage capacitive shunt RF-MEMS switch using a corrugated membrane with HRS MEMS packaging. Analytical analyses and experimental results have been carried out to derive algebraic expressions for the mechanical actuation mechanics of corrugated membrane for a low residual stress. It is shown that the residual stress of both types of corrugated and flat membranes can be modeled with the help of a mechanics theory. The residual stress in corrugated membranes is calculated using a geometrical model and is confirmed by finite element method(FEM) analysis and experimental results. The corrugated electrostatic actuated bridge is suspended over a concave structure of CPW, with sputtered nickel(Ni) as the structural material for the bridge and gold for CPW line, fabricated on high-resistivity silicon(HRS) substrate. The corrugated switch on concave structure requires lower actuation voltage than the flat switch on planar structure in various thickness bridges. The residual stress is very low by corrugating both ends of the bridge on concave structure. The residual stress of the bridge material and structure is critical to lower the actuation voltage. The Self-alignment HRS MEMS package of the RF-MEMS switch with a $15{\Omega}{\cdot}cm$ lightly-doped Si chip carrier also shows no parasitic leakage resonances and is verified as an effective packaging solution for the low cost and high performance coplanar MMICs.

• Korean Chemical Engineering Research
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• v.46 no.2
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• pp.402-407
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• 2008

Recent popularity in mobile electronics requires higher standard on the mechanical strength of electronic packaging. Thus, the method of soldering between chip and substrate in electronic packaging process is changing from conventional method using intermetallic compound to a new method using organic solderability preservative (OSP) in order to improve the stability and the reliability of final product. Since current organic solder preservatives have several serious problems like thermo-stability during packaging process, however, it is necessary to develop new OSPs having thermo-stability. The main purpose of this study is to investigate the effect of MeOH/IPA (Isopropyl alcohol) ratio on the fluxing of a new OSP, developed in previous research, andto find out an optimum formulation of flux components for the application of the OSP in current packaging process. As a result of this study, it was revealed that higher MeOH/IPA ratio in flux showed better performance of fluxing a new OSP.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.73-78
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• 2016

An increase in the transistor density of integrated circuit devices leads to a very high increase in heat dissipation density, which causes a long-term reliability and various thermal problems in microelectronics. In this study, liquid cooling method was investigated using straight microchannels with various metal bumps. Microchannels were fabricated on Si wafer using deep reactive ion etching (DRIE), and Ag, Cu, or Cr/Au/Cu metal bumps were placed on Si wafer by a screen printing method. The surface temperature of liquid cooling structures with various metal bumps was measured by infrared (IR) microscopy. For liquid cooling with Cr/Au/Cu bumps, the surface temperature difference before and after liquid cooling was $45.2^{\circ}C$ and the power density drop was $2.8W/cm^2$ at $200^{\circ}C$ heating temperature.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.83-88
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• 2018

The electromigration (EM) tests were performed at $150^{\circ}C$ with $1.5{\times}10^5A/cm^2$ conditions in order to investigate the effect of non-conductive film (NCF) trap on the electrical reliability of Cu/Ni/Sn-Ag microbumps. The EM failure time of Cu/Ni/Sn-Ag microbump with NCF trap was around 8 times shorter than Cu/Ni/Sn-Ag microbump without NCF trap. From systematic analysis on the electrical resistance and failed interfaces, the trapped NCF-induced voids at the Sn-Ag/Ni-Sn intermetallic compound interface lead to faster EM void growth and earlier open failure.