• 신재생에너지
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• 제5권1호
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• pp.26-31
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• 2009

The surface etching characteristics of single crystalline silicon wafer were investigated using potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). The saw damage layer was removed after 10min by KOH 45wt% solution at $80^{\circ}C$. The wafer etched at high temperature ($90^{\circ}C$) and in low concentration (4wt%) of TMAH solution showed an increased etch rate of silicon wafer and wavy patterns on the surface. Especially, pyramidal textures were formed in 4wt% TMAH solution without alcohol additives.

• Tribology and Lubricants
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• 제17권3호
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• pp.191-197
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• 2001

Nano adhesion and friction characteristics between SPM(scanning electron microscope) tips and flat plates of different materials were experimentally studied. Tests were performed to measure adhesion and friction in AFM(atomic force microscope) and LFM(lateral force microscope) modes in different conditions of relative humidity. Three different Si$_3$N$_4$ tips (rdaii : 15nm, 22nm and 50 nm) and three different flat plates of Si-wafer(100), W-DLC(tungsten-incorporated diamond-like carbon) and DLC were used. Results generally showed that adhesion and friction increased with the tip radius, and W-DLC and DLC surfaces were superior to Si-wafer. But the adhesion force of Si-wafer showed non linearity with the tip radius while W-DLC and DLC surfaces showed good correlation to the “JKR model”. It was found that high adhesion force between Si-wafer and a large radius of tip was caused by a capillary action due to the condensed water.

• 전자공학회논문지A
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• 제32A권3호
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• pp.134-142
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• 1995

We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1816-1821
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• 2003

The sapphire wafer for blue light emitting device was manufactured by the implementation of the chemical and mechanical polishing process. The surface polishing of crystalline sapphire wafer was characterized by zeta potential measurement. The reduction process with the alkali slurry provides the surface chemical reaction with sapphire atoms. The poly-urethane pad also provides the frictional force to take out the chemically-reacted surface layers. The surface roughness was measured by the atomic force microscope and the crystalline quality was characterized by the double crystal X -ray diffraction analysis.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2009년도 춘계학술대회 논문집
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• pp.239-241
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• 2009

DRIE(Deep Ion Reactive Etching) 공정은 실리콘 웨이퍼를 식각하는 기술로서 Si wafer 비아 홀 제조에 주로 사용되고 있다. 즉, DRIE 공정은 식각 및 보호층 증착을 반복함으로써 직진성 식각을 가능하게 하는 공정이다. 또한, 3차원 적층 실장에서 Si wafer 비아 홀에 결함없이 효과적으로 구리 충진을 하기 위해서는 직각형 via보다 경사벽을 가진 via가 형상적으로 유리하다. 본 연구에서는 3차원 적층을 위한 Si wafer 비아 홀의 결함 없는 효과적인 구리 충진을 위해, DRIE 공정을 이용하여 기존의 경사벽을 가지는 via 흘 형성 공정보다 더욱 효과적인 공정을 개발하였다.

• Transactions on Electrical and Electronic Materials
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• 제3권4호
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• pp.5-9
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• 2002

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. Especially, to achieve the higher density and greater performance, shallow trench isolation (STI)-CMP process has been attracted attention for multilevel interconnection as an essential isolation technology. Also, it was possible to apply the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). In this work, we determined the process margin with optimized process conditions to apply HSS STI-CMP process. Then, we evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions. The wafer-to-wafer thickness variation and day-by-day reproducibility of STI-CMP process after repeatable tests were investigated. Our experimental results show, quite acceptable and reproducible CMP results with a wafer-to-wafer thickness variation within 400$\AA$.

• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1224-1231
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• 2003

This paper reports on the air-gap type thin film bulk acoustic wave resonator(FBAR) using ultra thin wafer with thickness of 50$\mu\textrm{m}$. It was fabricated to realize a small size devices and integrated objects using MEMS technology for flexible microsystems. To reduce a error of experiment, MATLAB simulation was executed using material characteristic coefficient. Fabricated thin FBAR consisted of piezoelectric film sandwiched between metal electrodes. Used piezoelectric film was the aluminum nitride(AlN) and electrode was the molybdenum(Mo). Thin wafer was fabricated by wet etching and dry etching, and then handling wafer was used to prevent damage of FBAR. The series resonance frequency and the parallel frequency measured were 2.447㎓ and 2.487㎓, respectively. Active area is 100${\times}$100$\mu\textrm{m}$$^2$.Q-factor was 996.68 and K$^2$$\_$eff/ was 3.91％.

• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• 설비공학논문집
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• 제7권3호
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• pp.521-527
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• 1995

The average particle deposition velocity toward a vertical wafer surface in a vertical airflow chamber was measured by a wafer surface scanner(PMS Model SAS-3600). Polystyrene latex(PSL) spheres with diameters between 0.3 and $0.8{\mu}m$ were used. To examine the effect of the airflow velocity on the deposition velocity, experiments were conducted for three vertical airflow velocities ; 20, 30, 50cm/s. Experimental data of particle deposition velocity were compared with those given by prediction model suggested by Liu and Ahn(1987).

• 반도체디스플레이기술학회지
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• 제6권2호
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• pp.35-40
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• 2007

An integrated material removal model considering thermal, chemical and contact mechanical effects in CMP process is proposed. These effects are highly coupled together in the current modeling effort. The contact mechanics is employed in the model incorporated with the heat transfer and chemical reaction mechanisms. The mechanical abrasion actions happening due to the mechanical contacts between the wafer and abrasive particles in the slurry and between the wafer and pad asperities cause friction and consequently generate heats, which mainly acts as the heat source accelerating chemical reaction(s) between the wafer and slurry chemical(s). The proposed model may be a help in understanding multi-physical interactions in CMP process occurring among the wafer, pad and various consumables such as slurry.