• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.811-812
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• 2012

• IE interfaces
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• v.12 no.3
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• pp.437-447
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• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

• Journal of the Korea Society for Simulation
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• v.12 no.3
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• pp.13-20
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• 2003

Semiconductor Manufacturing has emerged as one of the most important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer

• Journal of the Korean Ceramic Society
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• v.34 no.7
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• pp.699-702
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• 1997

The cross sectional image of thin oxide failure of MOS device could be observed by Emission Microscope and Focused Ion Beam at the weak point. The oxide failures in low electric field was associated with the presence of a particle or abnormal pattern. The failures occuring at medium field are related to a pit of Si substrate. The pits could be originated from the microdefects of Cz Si wafer.

• Journal of the Korean Vacuum Society
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• v.14 no.2
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• pp.91-96
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• 2005

The silicon-on-insulator (SOI) wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by SRIM simulation that 65keV proton implantation is required for a SOI wafer (200nm SOI, 400nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the $6\~9\times10^{16}\;H^+/cm^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. Direct wafer bonding is performed by joining two wafers together after creating hydrophilic surfaces by a modified RCA cleaning, and IR inspection is followed to ensure a void free bonding. The wafer splitting was accomplished by annealing at the predetermined optimum condition, and high temperature annealing was then performed at $1,100^{\circ}C$ for 60 minutes to stabilize the bonding interface. TEM observation revealed no detectable defect at the SOI structure, and the interface trap charge density at the upper interface of the BOX was measured to be low enough to keep 'thermal' quality.

• Current Photovoltaic Research
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• v.2 no.3
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• pp.120-123
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• 2014

Thermal doping method using furnace is generally used for solar-cell wafer doping. It takes a lot of time and high cost and use toxic gas. Generally selective emitter doping using laser, but laser is very high equipment and induce the wafer's structure damage. In this study, we apply atmospheric pressure plasma for solar-cell wafer doping. We fabricated that the atmospheric pressure plasma jet injected Ar gas is inputted a low frequency (1 kHz ~ 100 kHz). We used shallow doping wafers existing PSG (Phosphorus Silicate Glass) on the shallow doping CZ P-type wafer (120 ohm/square). SIMS (Secondary Ion Mass Spectroscopy) are used for measuring wafer doping depth and concentration of phosphorus. We check that wafer's surface is not changed after plasma doping and atmospheric pressure doping width is broaden by increase of plasma treatment time and current.

• Tribology and Lubricants
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• v.35 no.3
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• pp.176-182
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• 2019

The primary objective of this study is to treat a monocrystalline silicon (Si) wafer having a thickness of $279{\mu}m$ by employing the ultrasonic nanocrystal surface modification (UNSM) technology for improving the efficiency and service life of nano-electromechanical systems (NEMSs) and micro-electromechanical systems (MEMSs) by enhancing of wear and corrosion resistances. The wear and corrosion resistances of the Si wafer were systematically investigated before and after UNSM treatment, wherein abrasive, oxidative and spalling wear mechanisms were applied to the as-received and subsequently UNSM-treated Si wafer. Compared to the asreceived state, the wear and corrosion resistances of the UNSM-treated Si wafer are found to be enhanced by about 23% and 14%, respectively. The enhancement in wear and corrosion resistances after UNSM treatment may be attributed to grain size refinement (confirmed by Raman spectroscopy) and modified surface integrity. Furthermore, it is observed that the Raman intensity reduced significantly after UNSM treatment, whereas neither the Raman shift nor new phases were found on the surface of the UNSM-treated Si wafer. In addition, the friction coefficient values of the as-received and UNSM-treated Si wafers are found to be about 0.54 and 0.39, respectively. Hence, UNSM technology can be effectively incorporated as an alternative mechanical surface treatment for NEMSs and MEMSs comprising Si wafers.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.171-176
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• 2021

Die-to-wafer (D2W) hybrid bonding in the multilayer semiconductor manufacturing process is one of wafer direct bonding, and various studies are being conducted around the world. A noteworthy point in the current die-to-wafer process is that a lot of voids occur on the bonding surface of the die during bonding. In this study, as a suggested method for removing voids generated during the D2W hybrid bonding process, a flexible mechanism for implementing convex for die bonding to be applied to the bond head is proposed. In addition, modeling of flexible mechanisms, analysis/design/control/evaluation of static/dynamics properties are performed. The proposed system was controlled by capacitive sensor (lion precision, CPL 290), piezo actuator (P-888,91), and dSpace. This flexure mechanism implemented a working range of 200 ㎛, resolution(3σ) of 7.276nm, Inposition(3σ) of 3.503nm, settling time(2%) of 500.133ms by applying a reverse bridge type mechanism and leaf spring guide, and at the same time realized a maximum step difference of 6 ㎛ between die edge and center. The results of this study are applied to the D2W hybrid bonding process and are expected to bring about an effect of increasing semiconductor yield through void removal. In addition, it is expected that it can be utilized as a system that meets the convex variable amount required for each device by adjusting the elongation amount of the piezo actuator coupled to the flexible mechanism in a precise unit.

• Korean Journal of Materials Research
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• v.32 no.9
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• pp.396-402
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• 2022

In this study, surface roughness and interfacial defect characteristics were analyzed after forming a high-k oxide film on the surface of a prime wafer and a test wafer, to study the possibility of improving the quality of the test wafer. As a result of checking the roughness, the deviation in the test after raising the oxide film was 0.1 nm, which was twice as large as that of the Prime. As a result of current-voltage analysis, Prime after PMA was 1.07 × 10 A/cm² and Test was 5.61 × 10 A/cm², which was about 5 times lower than Prime. As a result of analyzing the defects inside the oxide film using the capacitance-voltage characteristic, before PMA Prime showed a higher electrical defect of 0.85 × 10¹² cm^-2 in slow state density and 0.41 × 10¹³ cm^-2 in fixed oxide charge. However, after PMA, it was confirmed that Prime had a lower defect of 4.79 × 10¹¹ cm^-2 in slow state density and 1.33 × 10¹² cm^-2 in fixed oxide charge. The above results confirm the difference in surface roughness and defects between the Test and Prime wafer.

• Journal of the Korean Applied Science and Technology
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• v.16 no.1
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• pp.33-40
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• 1999

We used Cu as a representative of metals to be directly adsorbed on the bare Si surface and studied its removal DHF, DHF-$H_2O_2$ and BHF solution. It has been found that Cu ion in DHF adheres on every Si wafer surface that we used in our study (n, p, n+, p+) especially on the n+-Si surface. The DHF-$H_2O_2$ solution is found to be effective in removing metals featuring high electronegativity such as Cu from the p-Si and n-Si wafers. Even when the DHF-$H_2O_2$ solution has Cu ions at the concentration of 1ppm, the solution is found effective in cleaning the wafer. In the case the n+-Si and p+-Si wafers, however, their surfaces get contaminated with Cu When Cu ion of 10ppb remains in the DHF-$H_2O_2$ solution. When BHF is used, Cu in BHF is more likely to contaminate the n+-Si wafer. It is also revealed that the surfactant added to BHF improve wettability onto p-Si, n-Si and p+-Si wafer surface. This effect of the surfactant, however, is not observed on the n+-Si wafer and is increased when it is immersed in the DHF-$H_2O_2$ solution for 10min. The rate of the metallic contamination on the n+-Si wafer is found to be much higher than on the other Si wafers. In order to suppress the metallic contamination on every type of Si surface below 1010atoms/cm2, the metallic concentration in ultra pure water and high-purity DHF which is employed at the final stage of the cleaning process must be lowered below the part per trillion level. The DHF-$H_2O_2$ solution, however, degrades surface roughness on the substrate with the n+ and p+ surfaces. In order to remove metallic impurities on these surfaces, there is no choice at present but to use the $NH_4OH-H_2O_2-H_2O$ and $HCl-H_2O_2-H_2O$ cleaning.