• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.10
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• pp.68-76
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• 1997

In this paper, design parameters of rapid thermal processing(RTP) to minimize the wafer temperature uniformity errors are proposed. Lamp ring positions and the wafer height are important parameters for wafer temperature uniformity in RTP. We propose the method to seek lamp ring positions and the wafer gheight for optimal temperature uniformity. The proposed method is applied to seek optimal lamp ring positions and the wafer feight of 8 inch wafer. To seek the optimal lamp ring positions and the wafer height, we vary lamp ring positions and the wafer height and then formulate the wafer temperature uniformity problem to the linear programming problem. Finally, it is shown that the wafer temperature uniformity in RTP designed by optimal problem. Finally, it is hsown that the wafer temperature uniformity is RTP designed by optimal parameters is improved to comparing with RTP designed by the other method.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1068-1071
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• 2001

Recently, the minimum line width shows a tendancy to decrease and the multi-level to increase in semiconductor. Therefore, a planarization technique is needed, which chemical polishing(CMP) is considered as one of the most important process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as microscratches, abrasive contaminations, and non-uniformity of polished wafer edges. Spin Etching can improve the defects of CMP. It uses abrasive-free chemical solution instead of slurry. Wafer rotates and chemical solution is simultaneously dispensed on a whole surface of the wafer. Thereby chemical reaction is occurred on the surface of wafer, material is removed. On this study, TEOS film is removed by CMP and Spin Etching, the results are estimated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.484-487
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• 1997

The dicing is a process of gaining chip from a wafer. It is done by some mechanism to lengthwise and crosswise. Here, it is focused on measuring a depth of the wafer hefore a process of the dicing. First of all, it checks a precise outer position for the wafer on table to gain the chip. Second, the xafer should he lined after Imowing how much depth, it is in out of the outer position of the wafer. Here suggests that there are a composition of mechanical system, how to measure a depth out of scriber axis, a result from testing.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.1
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• pp.26-32
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• 2012

Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study will report the characteristic of wafer according to processing time, machining speed and pressure which have major influence on the abrasion of Si wafer polishing. It is possible to evaluation of wafer abrasion by load cell and infrared temperature sensor. The characteristic of wafer surface according to processing condition is selected to use a result data that measure a pressure, machining speed, and the processing time. This result is appeared by the characteristic of wafer surface in machining condition. Through that, the study cans evaluation a wafer characteristic in variable machining condition. It is important to obtain optimal condition. Thus the optimum condition selection of ultra precision Si wafer polishing using load cell and infrared temperature sensor. To evaluate each machining factor, use a data through each sensor. That evaluation of abrasion according to variety condition is selected to use a result data that measure a pressure, machining speed, and the processing time. And optimum condition is selected by this result.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.98-101
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• 2003

As the ultra precision grinding can be applied to wafering process by the refinement of the abrasive. the development of high stiffness equipment and grinding skill, the conventional wafering process which consists of lapping, etching, 1st, 2nd and 3rd polishing could be exchanged to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Futhermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focused on the flatness of the ground wafer. Generally, the ground wafer has concave profile because of the difference of wheel path density, grinding temperature and elastic deformation of the equiptment. Tilting mathod is applied to avoid such non-uniform material removes. So, in this paper, the geometric analysis on grinding process is carried out, and then, we can predict the profile of th ground wafer by using profile simulation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.5
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• pp.106-111
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• 2007

After the semiconductor processing, wafer is attracted by ESC(Electrostatic Chuck) with remaining electric charge. That causes too many problems for examples, sliding of wafer, popping or broken. This paper presents the model of ESC for silicon wafer, which is modeled by electrical circuit component such as capacitor. The simulations using PSpice result in the phenomenon of silicon wafer was charged by ESC. In this paper we suggest the discharging method. for wafer.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.10
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• pp.26-33
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• 2004

Ultra precision grinding technology has been developed from the refinement of the abrasive, the development of high stiffness equipment and grinding skill. The conventional wafering process which consists of lapping, etching, 1 st, 2nd and 3rd polishing has been changed to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Furthermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focuses on the flatness of the ground wafer. Generally, the ground wafer has concave pronto because of the difference of wheel path density, grinding temperature and elastic deformation of the equipment. Wafer tilting is applied to avoid non-uniform material removal. Through the geometric analysis of wafer grinding process, the profile of the ground wafer is predicted by the development of profile simulator.

• Journal of the Korean Ceramic Society
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• v.46 no.1
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• pp.30-34
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• 2009

A Sand blasting technology has been used to address via and trench processing of glass wafer of optic semiconductor packaging. Manufactured sand blast that is controlled by blast nozzle and servomotor so that 8" wafer processing may be available. 10mm sq test device manufactured by Dry Film Resist (DFR) pattern process on 8" glass wafer of $500{\mu}m's$ thickness. Based on particle pressure and the wafer transfer speed, etch rate, mask erosion, and vertical trench slope have been analyzed. Perfect 500 um tooling has been performed at 0.3 MPa pressure and 100 rpm wafer speed. It is particle pressure that influence in processing depth and the transfer speed did not influence.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.47-49
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• 2006

Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.