• 한국재료학회지
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• 제16권10호
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• pp.652-655
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• 2006

A direct wafer bonding process necessary for GaAs-on-insulator (GOI) fabrication with high thermal annealing temperatures was studied by using PECVD oxides between gallium arsenide and silicon wafers. In order to apply some uniform pressure on initially-bonded wafer pairs, a graphite sample holder was used for wafer bonding. Also, a tool for measuring the tensile forces was fabricated to measure the wafer bonding strengths of both initially-bonded and thermally-annealed samples. GaAs/$SiO_2$/Si wafers with 0.5-$\mu$m-thick PECVD oxides were annealed from $100^{\circ}C\;to\;600^{\circ}C$. Maximum bonding strengths of about 84 N were obtained in the annealing temperature range of $400{\sim}500^{\circ}C$. The bonded wafers were not separated up to $600^{\circ}C$. As a result, the GOI wafers with high annealing temperatures were demonstrated for the first time.

• 산업경영시스템학회지
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• 제46권2호
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• pp.1-12
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• 2023

To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.108-112
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• 2023

Precision manufacturing technology is rapidly developing due to the extreme miniaturization of semiconductor processes to comply with Moore's Law. Accurate and precise alignment, which is one of the key elements of the semiconductor pre-process and post-process, is very important in the semiconductor process. The center detection of wafer align marks plays a key role in improving yield by reducing defects and research on accurate detection methods for this is necessary. Methods for accurate alignment using traditional image sensors can cause problems due to changes in image brightness and noise. To solve this problem, engineers must go directly into the line and perform maintenance work. This paper emphasizes that the development of AI technology can provide innovative solutions in the semiconductor process as high-resolution image and image processing technology also develops. This study proposes a new wafer center detection method through variable thresholding. And this study introduces a method for detecting the center that is less sensitive to the brightness of LEDs by utilizing a high-performance object detection model such as YOLOv8 without relying on existing algorithms. Through this, we aim to enable precise wafer focus detection using artificial intelligence.

• Macromolecular Research
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• 제15권4호
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• pp.348-356
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• 2007

The aim of this study was to fabricate a submicro-and micro-patterned fibronectin coated wafer for a cell culture, which allows the positions and dimensions of the attached cells to be controlled. A replica molding was made into silicon via a photomask in quartz, using E-beam lithography, and then fabricated a polydimethylsiloxane stamp using the designed silicon mold. Hexadecanethiol $[HS(CH_2){_{15}}CH_3]$, adsorbed on the raised plateau of the surface of polydimethylsiloxane stamp, was contact-printed to form self-assembled monolayers (SAMs) of hexadecanethiolate on the surface of an Au-coated glass wafer. In order to form another SAM for control of the surface wafer properties, a hydrophilic hexa (ethylene glycol) terminated alkanethiol $[HS(CH_2){_{11}}(OCH_2CH_2){_6}OH]$ was also synthesized. The structural changes were confirmed using UV and $^1H-NMR$ spectroscopies. A SAM terminated in the hexa(ethylene glycol) groups was subsequently formed on the bare gold remaining on the surface of the Aucoated glass wafer. In order to aid the attachment of cells, fibronectin was adsorbed onto the resulting wafer, with the pattern formed on the gold-coated wafer confirmed using immunofluorescence staining against fibronectin. Fibronectin was adsorbed only onto the SAMs terminated in the methyl groups of the substrate. The hexa (ethylene glycol)-terminated regions resisted the adsorption of protein. Human dermal fibroblasts (P=4), obtained from newborn foreskin, only attached to the fibronectin-coated, methyl-terminated hydrophobic regions of the patterned SAMs. N-HDFs were more actively adhered, and spread in a pattern spacing below $14{\mu}m$, rather than above $17{\mu}m$, could easily migrate on the substrate containing spacing of $10{\mu}m$ or less between the strip lines.

• 산업공학
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• 제17권1호
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• pp.1-12
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• 2004

In a modern semiconductor device manufacturing industry, statistical bin limits on wafer level test bin data are used for minimizing value added to defective product as well as protecting end customers from potential quality and reliability excursion. Most wafer level test bin data show skewed distributions. By Monte Carlo simulation, this paper evaluates methods and sample size effect regarding determination of statistical bin limits. In the simulation, it is assumed that wafer level test bin data follow the Poisson distribution. Hence, typical shapes of the data distribution can be specified in terms of the distribution's parameter. This study examines three different methods; 1) percentile based methodology; 2) data transformation; and 3) Poisson model fitting. The mean square error is adopted as a performance measure for each simulation scenario. Then, a case study is presented. Results show that the percentile and transformation based methods give more stable statistical bin limits associated with the real dataset. However, with highly skewed distributions, the transformation based method should be used with caution in determining statistical bin limits. When the data are well fitted to a certain probability distribution, the model fitting approach can be used in the determination. As for the sample size effect, the mean square error seems to reduce exponentially according to the sample size.

• 한국멀티미디어학회논문지
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• 제16권6호
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• pp.782-794
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• 2013

본 논문에서는 카메라를 이용한 웨이퍼 위치 인식 알고리즘을 제안한다. 먼저 챔버 외부의 조명 반사와 카메라로 인한 영상의 원근 왜곡을 제거하기 위하여 투영 변환을 적용하여 실제 웨이퍼와 같이 정원의 형태로 복원한다. 다음, 에지 검출 알고리즘을 이용하여 웨이퍼의 외부 경계를 추출한 후, 일반화 대칭 변환을 적용하여 원을 검출함으로서 웨이퍼의 위치를 검사한다. 일반화 대칭 변환은 영상에서 화소쌍들 사이의 대칭값을 거리 가중치 함수, 위상 가중치 함수, 화소들의 기울기 크기와 로그 맵핑이 결합되어 영상에서 관심 영역을 추출한다. 제안하는 방법을 적용하여 웨이퍼가 올바른 위치에 장착되었는가를 검사하여 클리닝 시스템 장비와 웨이퍼의 파손을 미연에 방지한다.

• 한국신뢰성학회지:신뢰성응용연구
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• 제16권1호
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• pp.26-31
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• 2016

Purpose: The purpose of this study was to investigate the effect of grinding process and thickness on the fracture strength of silicon die used for semiconductor substrate. Method: Silicon wafers with different thickness from $200{\mu}m$ to $50{\mu}m$ were prepared by chemical mechanical polishing (CMP) and dicing before grinding (DBG) process, respectively. Fracture load was measured by point load test for 50 silicon dies per each wafer. Results: Fracture strength at the center area was lower than that at the edge area of the wafer fabricated by DBG process, while random distribution of the fracture strength was observed for the CMPed wafer. Average fracture strength of DBGed specimens was higher than that of the CMPed ones for the same thickness of wafer. Conclusion: DBG process can be more helpful for lowering fracture probability during the semiconductor fabrication process than CMP process.

• 반도체디스플레이기술학회지
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• 제21권2호
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• pp.51-56
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• 2022

Recently, the demand for semiconductors is expanded to various industries, and the use of high-quality and high-performance chips is increasing. With the trend, the diameter magnification and high integration of the semiconductor wafers are mandatory. As a result, there is a growing demand for the productivity improvement and the surface precision. There have been many studies on the stabilization of the wafer manufacturing processes in order to satisfy those specifications. Many complaints have been appealed by the wafer buyers that there are many unacceptable wafers with surface defects and foreign material adhesion which are caused by the vibrations during transportation. This study intends to derive the material improvement of the packing box of the wafers to suppress the vibrations of the box, and eventually to reduce the surface defects and the foreign material adhesion. The result shows that optimal material can substantially decrease the vibration of the packing box.

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.23-28
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• 2009

Si 기판의 캐비티 형성이 불필요한 웨이퍼-레벨 MEMS capping 공정을 연구하였다. 4인치 Si 웨이퍼에 Ni 캡을 전기도금으로 형성하고 Ni 캡 rim을 Si 하부기판의 Cu rim에 에폭시 본딩한 후, SnBi debonding 층을 이용하여 상부기판을 Ni 캡 구조물로부터 debonding 하였다. 진공증착법으로 형성한 SnBi debonding 층은 Bi와 Sn 사이의 심한 증기압 차이에 의해 Bi/Sn의 2층 구조로 이루어져 있었다. SnBi 증착 층을 $150^{\circ}C$에서 15초 이상 유지시에는 Sn과 Bi 사이의 상호 확산에 의해 eutectic 상과 Bi-rich $\beta$상으로 이루어진 SnBi 합금이 형성되었다. $150^{\circ}C$에서 유지시 SnBi의 용융에 의해 Si 기판과 Ni 캡 구조물 사이의 debonding이 가능하였다.

• 마이크로전자및패키징학회지
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• 제25권1호
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• pp.41-45
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• 2018

기술의 발전과 전자기기의 소형화와 함께 반도체의 크기는 점점 작아지고 있다. 이와 동시에 반도체 성능의 고도화가 진행되면서 입출력 단자의 밀도는 높아져 패키징의 어려움이 발생하였다. 이러한 문제를 해결하기 위한 방법으로 산업계에서는 팬아웃 웨이퍼 레벨 패키지(FO-WLP)에 주목하고 있다. 또한 FO-WLP는 다른 패키지 방식과 비교해 얇은 두께, 강한 열 저항 등의 장점을 가지고 있다. 하지만 현재 FO-WLP는 생산하는데 몇 가지 어려움이 있는데, 그 중 한가지가 웨이퍼의 휨(Warpage) 현상의 제어이다. 이러한 휨 변형은 서로 다른 재료의 열팽창계수, 탄성계수 등에 의해 발생하고, 이는 칩과 인터커넥트 간의 정렬 불량 등을 야기해 대량생산에 있어 제품의 신뢰성 문제를 발생시킨다. 이러한 휨 현상을 방지하기 위해서는 패키지 재료의 물성과 칩 사이즈 등의 설계 변수의 영향에 대해 이해하는 것이 매우 중요하다. 이번 논문에서는 패키지의 PMC 과정에서 칩의 두께와 EMC의 두께가 휨 현상에 미치는 영향을 유한요소해석을 통해 알아보았다. 그 결과 특정 칩과 EMC가 특정 비율로 구성되어 있을 때 가장 큰 휨 현상이 발생하는 것을 확인하였다.