• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.149-152
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• 2004

Generally the wafer is increased by 300mm. We are desired that the wafer is prevented from pollutions of metal contaminant on surface of wafer. We have to develop new wafer cleaning process of IC Manufacturing that can reduce DI water and chemical by removal of the wafer cleaning process step. Moreover, it is difficult to control temprature and density of chemical in spite of rapidly increasing automation of system. We design smart module controller for new generation of semiconductor wet station with intelligent algorithm using data that is taken by computer simulation for optimal system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.6
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• pp.647-653
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• 1988

A rapid thermal annealing system using tungsten halogen lamp has been designed and assembled. A control scheme where the temperature control is executed with calculated wafer temperature by considering the thermocouple delay rather than measured thermocouple temperature,is proposed. This control scheme gives more accurate control of the wafer temperature. In addition, the distribution of transmitted light power to the wafer in the system has been simulated, and lamp interval modification has been able to give more uniform light power distribution. Considering incident light spectrum, absorption, reflection, radiation of silicon, etc., temperature profile has been simulated. When the light power uniformity on the 3" wafer is below 1%, the temperature uniformity is about 2%.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.10a
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• pp.502-506
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• 1999

Recently, the miniature of electric products such as notebook, cellular-phone etc. is apparently appeared, due to the smaller size of the semiconductor chips. As the size of chip gets smaller, the circuit could be easily damaged by the slightest influence, so it is important to control the chipping generation in the process of dicing. This paper deals with chipping of the silicon wafer dicing. The relationships between the dicing force and the wafer chipping are investigated. It is confirmed that the wafer chipping increases as the dicing force increases.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.3
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• pp.53-58
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• 2008

This study was conducted to evaluate the flatness of the porous type of dicing chuck. Two measurement systems for a vacuum chuck with a porous type of ceramic plate were prepared using a digital indicator and a laser interferometer. 6 inch of silicon and glass wafer were also used. Vacuum pressure from 100mmHg to 700mmHg by 100mmHg was increased. From experiments, chucked-wafer flatness was converged to the dicing chuck flatness itself even though the repeatability of contact method using indicator was unstable. Finally, the chuck flatness was estimated below $2{\mu}m$ with peak-to valley value.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.1
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• pp.85-91
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• 2004

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by chemical and mechanical polishing process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of sapphire crystalline wafer at surfaces has a full width at half maximum of 89 arcsec. The surfaces of sapphire wafer were mechanically affected by residual stress during the polishing process. The wave pattern of optical interference of sapphire wafer implies higher abrasion rate in the edge of the wafer than its center from the Newton's ring.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.1
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• pp.13-16
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• 2000

Progress in Si crystal and wafer technologies is discussed on single crystal growth, wafer fabrication, epitaxial growth, gettering, 300 mm and SOI. As for bulk crystal growth, the mechanism of grown-in defects (voids) formation, the succes of grown-in defect free crystal growth technology and nitrogen doped crystal are shown. New wafer fabrication technologies such as both-side mirror polishing and etchingless process have been developed. The epitaxial growth of SiGe/Si heterostructure for high speed bipolar device is treated. Gettering technology under low temperature process such as RTP is important, and also it is shown that IG effect for Ni could be predicted using computer simulation of precipitate density and size. The development of 300 mm wafer and SOI has made progress steadily.

• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.63-69
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• 2012

As decreasing size of chips, the need of wafer level packaging is increased in semi-conductor and display industries. Temperature uniformity is a crucial factor in vacuum soldering process to guarantee quality of bonding between chips and wafer. In this paper, a stepwise iterative algorithm has been suggested to obtain output profile of each heat source. Since this algorithm is based on open-loop stepwise iterative experimental technique, it is easier to implement and cost effective than real time feedback controls. Along with some experiments, it was shown that the suggested algorithm can remarkably improve temperature uniformity of wafer during whole heating process compared with the ordinary manual trial-and error method.

• Journal of the Semiconductor & Display Technology
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• v.11 no.3
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• pp.1-6
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• 2012

In this paper, inspection system based on optical scanning mechanism is designed and developed for solar cell wafer. It consists of optical scanning mechanism, NIR camera optics, machinery and control system, algorithm of defect detection and software. Optical scanning mechanism is composed of geometrical camera optics and structured hybrid illumination system. It is used to inspection of surface defects. NIR camera optics is used for inspection of defects inside solar cell wafer. It is shown that surface and internal micro defects can be detected in developed inspection system for solar cell wafer.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.7
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• pp.1434-1437
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• 2011

Precision measurement of silicon wafer resistivity has been using single-configuration Four-Point Probe(FPP) method. This FPP method have to applying sample size, shape and thickness correction factor for a probe pin spacing to precision measurement of silicon wafer. The deference for resistivity measurement values applied correction factor and not applied correction factor was about 1.0 % deviation. The sample size, shape and thickness correction factor for a probe pin spacing have an effects on precision measurement for resistivity of silicon wafer.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.86-90
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• 2018

Standards related to express the non-flatness of a wafer are reviewed and discussed, for example, bow, warp, and sori. Novel wafer warpage measurement method is proposed for 3D stacked IC application. The new way measures heat transfer from a heater to a wafer, which is a function of the contact area between these two surfaces and in turn, this contact area depends on the wafer warpage. Measurement options such as heating from room temperature and cooling from high temperature were experimentally examined. The heating method was found to be sensitive to environmental conditions. The cooling technique showed more robust and repeatable results and the further investigation for the optimal cooling condition is underway.