• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• Journal of Sensor Science and Technology
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• v.27 no.5
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• pp.300-305
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• 2018

The uncooled microbolometer thermal sensor for low cost and mass volume was designed to target the new infrared market that includes smart device, automotive, energy management, and so on. The microbolometer sensor features 80x60 pixels low-resolution format and enables the use of wafer-level vacuum packaging (WLVP) technology. Read-out IC (ROIC) implements infrared signal detection and offset correction for fixed pattern noise (FPN) using an internal digital to analog convertor (DAC) value control function. A reliable WLVP thermal sensor was obtained with the design of lid wafer, the formation of Au80%wtSn20% eutectic solder, outgassing control and wafer to wafer bonding condition. The measurement of thermal conductance enables us to inspect the internal atmosphere condition of WLVP microbolometer sensor. The difference between the measurement value and design one is $3.6{\times}10-9$ [W/K] which indicates that thermal loss is mainly on account of floating legs. The mean time to failure (MTTF) of a WLVP thermal sensor is estimated to be about 10.2 years with a confidence level of 95 %. Reliability tests such as high temperature/low temperature, bump, vibration, etc. were also conducted. Devices were found to work properly after accelerated stress tests. A thermal camera with visible camera was developed. The thermal camera is available for non-contact temperature measurement providing an image that merged the thermal image and the visible image.

• International Journal of Quality Innovation
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• v.8 no.2
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• pp.132-146
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• 2007

Constructing an effective production control policy is the most important issue in wafer fabrication factories. Most of researches focus on the input regulations of wafer fabrication. Although many of these policies have been proven to be effective for wafer fabrication manufacturing, in practical, there is a need to help operators decide which lots should be pulled in the right time and to develop a systematic way to alleviate the long queues at the bottleneck workstation. The purpose of this study is to construct a photolithography workstation dispatching rule (PADR). This dispatching rule considers several characteristics of wafer fabrication and influential factors. Then utilize the weights and threshold values to design a hierarchical priority rule. A simulation model is also constructed to demonstrate the effect of the PADR dispatching rule. The PADR performs better in throughput, yield rate, and mean cycle time than FIFO (First-In-First-Out) and SPT (Shortest Process Time).

• Journal of Environmental Health Sciences
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• v.37 no.1
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• pp.12-21
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• 2011

The objective of this study is to review retrospective exposure assessment methods used in wafer fabrication operations to determine whether adverse health effects including mortality or cancer incidence are related to employment in particular work activities and to recommend an appropriate approach for retrospective exposure assessment methods for epidemiological study. The goal of retrospective exposure assessment for such studies is to assign each study subject to a workgroup in such a way that differences in exposure within the workgroups are minimized, as well as to maximize the contrasts in exposure between workgroups. To reduce the misclassification of exposure and to determine if adverse health effects including mortality or cancer incidence are related to particular work activities of wafer fabrication workers, a minimum requirement of work history information on the wafer manufacturing eras, job and department at which they were exposed should be assessed. Retrospective assessment of the task that semiconductor workers performed should be conducted to determine not only the effect of a particular job on the development of adverse health effects including mortality or cancer incidence, but also to adjust for the healthy worker effect. In order to identify specific hazardous agents that may cause adverse health effects, past exposure to a specific agent or agent matrices should also be assessed.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.128-128
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• 2010

In this study, we investigated the evolution and reduction of the surface roughness during the high-speed chemical dry thinning process of Si wafers. The direct injection of NO gas into the reactor during the supply of F radicals from NF3 remote plasmas was very effective in increasing the Si thinning rate, due to the NO-induced enhancement of the surface reaction, but resulted in the significant roughening of the thinned Si surface. However, the direct addition of Ar and N2 gas, together with NO gas, decreased the root mean square (RMS) surface roughness of the thinned Si wafer significantly. The process regime for the increasing of the thinning rate and concomitant reduction of the surface roughness was extended at higher Ar gas flow rates. In this way, Si wafer thinning rate as high as $20\;{\mu}m/min$ and very smooth surface roughness was obtained and the mechanical damage of silicon wafer was effectively removed. We also measured die fracture strength of thinned Si wafer in order to understand the effect of chemical dry thinning on removal of mechanical damage generated during mechanical grinding. The die fracture strength of the thinned Si wafers was measured using 3-point bending test and compared. The results indicated that chemical dry thinning with reduced surface roughness and removal of mechanical damage increased the die fracture strength of the thinned Si wafer.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.2
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• pp.1-6
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• 2008

In recent years, developments in the semiconductor and electronic industries have brought a rapid increase in the use of large size silicon wafer. For further improvement of the ultra precision surface and flatness of Si wafer necessary to high density ULSI, it is known that polishing is very important. However, most of these investigation was experiment less than 300mm diameter. Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study reports the machining variables that has major influence on the characteristic of wafer polishing. It was adapted to polishing pressure, machining speed, and the slurry mix ratio, the optimum condition is selected by ultra precision wafer polishing using load cell and infrared temperature sensor. The optimum machining condition is selected a result data that use a pressure and table speed data. By using optimum condition, it achieves a ultra precision mirror like surface.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.2
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• pp.111-123
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• 2019

In this paper, we propose a method for defining the input termination for on-wafer-type device under test (DUT) measurement. Using the newly defined input termination and noise wave correlation matrix (NWCM) measurement method based on noise power ratio, the NWCM of the on-wafer-type DUT was measured. We demonstrate a noise measurement configuration that includes wafer probes and bias tees to measure the on-wafer DUT. The S-parameter of the adapter that combines the bias tee, probe, and a line terminated by open is required to define the input termination for on-wafer DUT measurement. To measure the S-parameter of the adapter, a 2-port S-parameter measurement method using 1-port measurement is introduced. Using the measured S-parameters, a method for defining the new input termination for on-wafer-type DUT measurement is applied. The proposed method involves the measurement of the NWCM of the chip with a 1.5 dB noise figure. The noise parameters of the chip were obtained using the measured NWCM. The results indicate that the obtained values of the noise parameters are similar to those mentioned on a datasheet for the chip. In addition, repeated measurements yielded similar results, thereby confirming the reliability of the measurements.

• Journal of Mechanical Science and Technology
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• v.20 no.6
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• pp.738-747
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• 2006

The friction behaviour of Si-wafer, diamond-like carbon (DLC) and two self-assembled monolayers (SAMs) namely dimethyldichlorosilane (DMDC) and diphenyl-dichlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer In-terestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly Influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains.

• Transactions of the Society of Information Storage Systems
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• v.2 no.2
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• pp.96-99
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• 2006

In this research, a wafer-level transfer method of cantilever away on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.2
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• pp.62-67
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• 2000

The uniformity of temperature on a wafer is one of the most important parameters to control the RTP (Rapid Thermal Process) with proper input signals. Since it is impossible to achieve the uniformity of temperature without exact estimation of temperature at all points on the wafer, the difficulty of understanding internal dynamics and structural complexities of the RTP is a primary obstacle to accurately measure the distributed temperatures on the wafer. Furthermore, it is also hard to accomplish desirable estimation because only few pyrometers have been commonly available in the general equipments. In the paper, a thermal model based on the chamber geometry of the AST SHS200 RTP system is developed to effectively control the thermal uniformity on the wafer. First of all, the estimation method of one-point measurement is developed, which is properly extended to the case of multi-point measurements. This thermal model is validated through certain simulation and experiments. The work can be usefully contributed to building a run-by-run or a real-time controls of the RTP.