• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.4
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• pp.251-255
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• 2021

a-Si is commonly considered as a primary candidate for the formation of passivation layer in heterojunction (HIT) solar cells. However, there are some problems when using this material such as significant losses due to recombination and parasitic absorption. To reduce these problems, a wide bandgap material is needed. A wide bandgap has a positive influence on effective transmittance, reduction of the parasitic absorption, and prevention of unnecessary epitaxial growth. In this paper, the adoption of a-SiO_x:H as the intrinsic layer was discussed. To increase lifetime and conductivity, oxygen concentration control is crucial because it is correlated with the thickness, bonding defect, interface density (D_it), and band offset. A thick oxygen-rich layer causes the lifetime and the implied open-circuit voltage to drop. Furthermore the thicker the layer gets, the more free hydrogen atoms are etched in thin films, which worsens the passivation quality and the efficiency of solar cells. Previous studies revealed that the lifetime and the implied voltage decreased when the a-SiOx thickness went beyond around 9 nm. In addition to this, oxygen acted as a defect in the intrinsic layer. The D_it increased up to an oxygen rate on the order of 8%. Beyond 8%, the D_it was constant. By controlling the oxygen concentration properly and achieving a thin layer, high-efficiency HIT solar cells can be fabricated.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.109-117
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• 2004

In this paper, a K-band local oscillator composed of a VCDRO(Voltage Controlled Dielectric Resonator Oscillator), GaAs MESFET, and Reflector type frequency doubler has been designed and fabricated. TO obtain a good phase noise performance of a VCDRO, a active device was selected with a low noise figure and a low flicker noise MESFET and a dielectric resonator was used for selecting stable and high oscillation frequency. Especially, to have a higher conversion gain than a conventional doubler as well as a good harmonic suppression performance with circuit size reduced a doubler structure was employed as the Reflector type composed of a reflector and a open stub of quarter wave length for rejecting the unwanted harmonics. The measured results of fabricated oscillator show that the output power was 5.8 dBm at center frequency 12.05 GHz and harmonic suppression -37.98 dBc, Phase noise -114 dBc at 100 KHz offset frequency, respectively, and measured results show of fabricated frequency doubler, the output power at 5.8 dBm of input power is 1.755 dBm conversion gain 1.482 dB, harmonic suppression -33.09 dBc, phase noise -98.23 dBc at 100 KHz offset frequency, respectively. This oscillator could be available to a local oscillator in K-band which used frequency doubler techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1982-1990
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• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.74-80
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• 2006

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• Journal of Sensor Science and Technology
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• v.9 no.3
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• pp.196-202
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• 2000

In this paper, we proposed the new bridge combination detection method for three dimensional piezoresistive silicon accelerometer, and the accelerometer with SOI structures was fabricated by bulk micromachining technology for using higher temperature than $200^{\circ}C$. The sensitivities of fabricated accelerometer for X, Y and Z-axis acceleration were about 8mV/V G, 8mV/V G and 40mV/V G. The nonlinearity of the output voltage was 1.6%FS and cross-axis sensitivity was within 4.6%. We confirmed that the three bridges detection method is very simple and the output characteristics of this accelerometer were similar to arithmetic circuit method accelerometer. The temperature characteristics of SOI structure accelerometer showed high operating temperature and good stability. And the temperature coefficient of offset voltage and sensitivity were $1033ppm^{\circ}C^{-1}$ and $1145ppm^{\circ}C$ respectively.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of Navigation and Port Research
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• v.27 no.5
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• pp.513-517
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• 2003

In this paper, a VCDRO(Voltage Control Dielectric Resonator Oscillator} applied to X-band as stable source is implementea and constructed with a MESFET for low noise, a dielectric resonator of high frequency selectivity and high Q varactor diode to obtain a good phase noise performance and stable sweep characteristics. The designed circuits is simulated through the harmonic balance simulation technique to provide the optimum performance. The measured results of a fabricated VCDRO show that output is 2.22dBm at 12.05GHz. harmonic suppression -30dBc. phase noise -130dBc at 100kHz offset. and sweep range of varactor diode $\pm$18.7MHz. respectively. This oscillator will be available to X-band application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1184-1189
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• 2004

A new schematic of quadrature voltage controlled oscillator(QVCO) is designed and fabricated. To obtain quadrature characteristic and low phase noise simultaneously, two differential VCOs are forced to un in quadrature mode by using coupling amplifier with a source degeneration resistor, which is optimized to obtain quadrature accuracy with minimum phase noise degradation. The designed QVCO was fabricated in standard CMOS technology. The measured performance showed the phase noise of below -120 dBc/Hz at 1 MHEz frequency offset, tuning bandwidth of 210 MHz from 2.34 GHz to 2.55 GHz with a tuning voltage varying form 0 to 1.8 V Quadrature error of 0.5 degree and amplitude error of 0.2 dB was measured with conjunction with low-lF mixer. The fabricated QVCO requires 19 mA including 5 mA in the VCO core part fiom a 1.8 V supply.