• Journal of the Korean Society for Precision Engineering
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• v.15 no.8
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• pp.46-59
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• 1998

This paper presents shape design, surface construction, and cutting path generation for the surface of marine ship propeller blades. A propeller blade should be designed to satisfy performance constraints that include operational speed which impacts rotations per minutes, stresses related to deliverable horst power, and the major length of the marine ship which impacts the blade size and shape characteristics. Primary decision variables that affect efficiency in the design of a marine ship propeller blade are the blade diameter and the expanded area ratio. The blade design resulting from these performance constraints typically consists of sculptured surfaces requiring four or five axis contoured machining. In this approach a standard blade geometry description consisting of blade sections with offset nominal points recorded in an offset table is used. From this table the composite Bezier surface geometry of the blade is created. The control vertices of the Hazier surface patches are determined using a chord length fitting procedure from tile offset table data. Cutter contact points and path intervals are calculated to minimize travel distance and production time while maintaining a cusp height within tolerance limits. Long path intervals typically generate short tool paths at the expense of increased however cusp height. Likewise, a minimal tool path results in a shorter production time. Cutting errors including gouging and under-cut, which are common errors in machining sculptured surfaces, are also identified for both convex and concave surfaces. Propeller blade geometry is conducive to gouging. The result is a minimal error free cutting path for machining propeller blades for marine ships.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.3
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• pp.1-10
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• 2000

This paper proposes a novel video coding system with rate control based on fractal algorithm To overcome the demerits of excessive amounts of coded bit generated by previous fractal coding methodology. the proposed system classifies the Image into three classes such as background, motion compensation, and fractal coding area. The motion vector for motion compensation, and the fractal offset value that is difference value between the predicted offset and the least-square approximated value are coded with variable length code The decision method which determines threshold value of partitioning quadtree is applied to the bit-rate control algorithm considering the quantity of currently generated bits and fixed channel bandwidth Experimental result shows that the proposed system enhances compression ratio 1.8 times higher than previous method for the same image quality, and performs efficient rate control for fixed channel bandwidth.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.839-846
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• 2011

Link Adaptation should select the best modulation and coding scheme (MCS) which gives the highest throughput as channel conditions vary. Several link adaptation algorithms for wireless local area network (WLAN) have been proposed but for the future WLAN systems such as 802.11n system, these algorithms do not guarantee the best performance. In this paper, we propose a new link adaptation algorithm in which an MCS level is chosen by the received SNR plus the offset value obtained from the transmission results. The performance of proposed algorithm is simulated by an IEEE 802.11n system. From the analysis, we conclude the proposed algorithm performs better than the well-known link adaptation algorithms such as auto rate fallback and general SNR-based techniques. Particularly, the proposed algorithm improves throughput when the packet error ratio (PER) is constrained for fast fading channels.

• ETRI Journal
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• v.36 no.1
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• pp.12-21
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• 2014

In this paper, we propose a new digital blind in-phase/quadrature-phase (I/Q) mismatch compensation technique for image rejection in a direct-conversion receiver (DCR). The proposed image-rejection circuit adopts DC offset cancellation and a sign-sign least mean squares (LMS) algorithm with a unique step size adaptation both for a fast and precise I/Q mismatch estimation. In addition, several performance-optimizing design considerations related to accuracy, speed, and hardware simplicity are discussed. The implementation of the proposed circuit in an FPGA results in an image-rejection ratio (IRR) of 65 dB, which is the best performance with modulated signals, along with an adaptation time of 0.9 seconds, which is a tenfold increase in the compensation speed as compared to previously reported circuits. The proposed technique will be a promising solution in the area of image rejection to increase both the speed and accuracy of future DCRs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.3
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• pp.395-403
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• 2014

This paper presents a new approach to improve the signal to noise ratio (SNR) for local seismic disaster preventing system in densely populated area. The seismic data measured in the local site includes various sensing noises (offset or measurement noise) and man-made/natural noises (road and rail traffic noise, rotating or hammering machinery noise, human activity noise such as walking and running, wind/atmospheric pressure-generated noise, etc.). These additive noises are different in time and frequency characters. The proposed method uses 3-stages processing to reduce these different additive noises. In the first stage, misalignment offset noise are diminished by time average processing, and then the second and third stages, coherent/incoherent noises such as man-made/natural noises are suppressed by array stacking. In addition, we derived the theoretical equation of the SNR gain improved by the proposed method. To evaluate the performance of the proposed method, computer simulations were performed with real seismic data and test equipment generated data as the input.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.289-294
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• 2010

In the vehicle communication system, transferred information is needed to be detected as possible as fast in order to inform car status located in front and rear side. Through the moving vehicle information, we can avoid the crash caused by sudden break of front one or acquire to real time traffic data to check the detour road. To be connecting the wireless communication between the vehicles, fast timing synchronization can be a key factor. Finding out the sync point fast is able to have more marginal time to compensate the distorted signals caused by channel variance. Thus, we introduce the combination method which helps find out the start of frame quickly. It is executed by auto-correlation and cross-correlation simultaneously using only short preambles. With taking the absolute value at the implemented synch block output, the proposed method shows much better system performance to us.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• International journal of advanced smart convergence
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• v.9 no.1
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• pp.172-176
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• 2020

The implementation of a low phase noise voltage controlled oscillator (VCO) is important for the signal integrity of wireless communication terminal. A low phase noise wideband VCO for a wireless local area network (WLAN) application is presented in this paper. A 6-bit coarse tune capacitor bank (capbank) and a fine tune varactor are used in the VCO to cover the target band. The simulated oscillation frequency tuning range is from 8.6 to 11.6 GHz. The proposed VCO is desgned using 65 nm CMOS technology with a high quality (Q) factor bondwire inductor. The VCO is biased with 1.8 V VDD and shows 9.7 mA current consumption. The VCO exhibits a phase noise of -122.77 and -111.14 dBc/Hz at 1 MHz offset from 8.6 and 11.6 GHz carrier frequency, respectively. The calculated figure of merit(FOM) is -189 dBC/Hz at 1 MHz offset from 8.6 GHz carrier. The simulated results show that the proposed VCO performance satisfies the required specification of WLAN standard.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.160-165
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• 2009

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 mV without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a $0.18{\mu}m$ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of $0.12\;mm^2$ consumes 3.6 m W at 2 MS/s and 3.3 V (analog)/1.8 V (digital).

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.286-288
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• 2007

In this paper, the fast locking PLL Frequency Synthesizer with low phase noise in a 0.18um CMOS process is presented. Its main application IS for the 915MHz ISM band wireless transponder upon the CPFSK (Continuous Phase Frequency Shift Keying) modulation scheme. Frequency synthesizer, which in this paper, is designed based on self-biased techniques and is independent with processing technology when damping factor and bandwidth fixed to most important parameters as operating frequency ratio, broad frequency range, and input phase offset cancellation. The proposed frequecy synthesizer, which is fully-integrated and is in 320M $^{\sim}$ 960MHz of the frequency range with 10MHz of frequency resolution. And its is implemented based on integer-N architecture. Its power consumption is 50mW at 1.8V of supply voltage and core area is $540{\mu}m$ ${\times}$ $450{\mu}m$. The measured phase noises are -117.92dBc/Hz at 10MHz offset, with low settling time less than $3.3{\mu}s$.