• Title/Summary/Keyword: OTS 처리 $SiO_2$ 절연막

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Electrical properties of $SiO_2$ thin film by OTS treatment (OTS 처리된 $SiO_2$ 박막의 전기적인 특성)

  • Kim, Jong-Wook;Oh, Teresa;Kim, Hong-Bae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.169-170
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    • 2007
  • 기존 사용되어온 절연막인 $SiO_2$ 의 절연특성이 신호의 간섭 등의 문제가 있어서 절연특성을 좋게 하기 위해 낮은 유전상수와 비결정질의 절연막을 요구하고 있다. 본 연구에서는 혼합된 OTS solution으로 처리된 $SiO_2$ 절연막이 OTS 함유량 증가에 따른 전기적인 특성을 조사하였다. 전압-전류 특성 곡선에 의한 누설전류 증가랑이 OTS 함유량 증가에 따라 비례적으로 증가하지 않았으며 0.7% 처리 농도에서 누설전류가 가장 적게 나타났다.

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Correlation between Leakage Current of Organic Treated Insulators and Grain Size of Pentacene Deposited film (유기물 처리 절연막의 누설전류 및 펜타센 증착 표면에 생긴 그레인 크기 사이의 상관관계)

  • Oh Teresa;Kim Hong-Bae;Son Jae-Gu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.6 s.348
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    • pp.18-22
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    • 2006
  • The inspection of surface properties under n-octadecyltrichlorosilane treated $SiO_2$ film was carried out by current-voltage characteristic and the scanning electron microscope. The voltage at zero current in low electric field is the lowest at 0.3 % OTS treated $SiO_2$ film with hybrid type. $SiO_2$ films changed from inorganic to hybrid or organic properties according to the increase of OTS content. OTS treated $SiO_2$ films with hybrid properties decreased the leakage currents, and the grain size of pentacene deposited sample was also the most small at the hybrid properties. The perpendicular generation of pentacene molecular was related with the surface of insulators. The surface with hybrid properties decreased the grain size, but that with inorganic or organic properties increased the grain size.

결합구조의 변화에 따른 유기물 박막의 특성분석

  • ;Kim Hong-Bae
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2006.05a
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    • pp.101-104
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    • 2006
  • 유기물 박막에서 누설전류의 크기는 트랜지스터의 성능과 관련된 중요한 요소이다. 일반적으로 사용되고 있는 반도체 소자에서의 절연 막으로서 $SiO_2$ 표면을 유기물로 처리하여 $SiO_2$ 박막 표면의 화학적 반응에 대하여 FTIR 분석법을 이용하여 조사하였다. $1100cm^{-1}$에서 $1570cm^{-1}$까지의 주픽에 대하여 분석한 결과, OTS처리함량에 따라서 샘플의 $Si-CH_3$ 픽의 함량이 증가하는 것을 알 수 있었으며, 0.7%의 샘플에서 급격한 변화가 일어나고 있다는 것을 확인하였다.

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Performance enhancement of Organic Thin Film Transistor by Ar Ion Beam treatment (Ar Ion Beam 처리를 통한 Organic Thin Film Transistor의 성능향상)

  • Jung, Suk-Mo;Park, Jae-Young;Yi, Moon-Suk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.15-19
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    • 2007
  • This paper reports the effects of Ar ion beam surface treatment on a $SiO_2$ dielectric layer in organic thin film transistors. We compared the electrical properties of pentacene-based OTFTs, treated by $O_2$ plasma or Ar ion beam treatments and characterized the states of the surface of the dielectric by using atomic force microscopy and X-ray photoelectron spectroscopy. For the sample which received $O_2$ plasma treatment, the mobility increased significantly but the on/off current ratio was found very low. The Ar ion beam-treated sample showed a very high on/off current ratio as well as a moderately improved mobility. XPS data taken from the dielectric surfaces after each of treatments exhibit that the ratio of between Si-O bonds and O-Si-O bonds was much higher in the $O_2$ plasma treated surface than in the Ar ion beam treated surface. We believe that our surface treatment using an inert gas, Ar, carried out an effective surface cleaning while keeping surface damage very low, and also the improved device performances was achieved as a consequence of improved surface condition.

A STUDY ON THE ELECTRICAL CHARACTERISTICS OF ORGANIC THIN FILM TRANSISTORS WITH SURFACE-TREATED GATE DIELECTRIC LAYER (표면 처리한 $SiO_2$를 게이트 절연막으로 하는 박막 트랜지스터의 특성 연구)

  • Lee, Jae-Hyuk;Lee, Yong-Soo;Park, Jae-Hoon;Choi, Jong-Sun;Kim, Eu-Gene
    • Proceedings of the KIEE Conference
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    • 2000.11c
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    • pp.455-457
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    • 2000
  • In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces, where the gate dielectrics were treated by the two methods which are the deposition of Octadecyltrichlorosilane (OTS) on the insulator and rubbing the insulator surface. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-7}$ Torr and at a deposition rate of $0.3{\AA}/sec$. Aluminum and gold were used for the gate and source/drain electrodes. OTS is used as a self-alignment layer between $SiO_2$ and pentacene. The gate dielectric surface was rubbed before pentacene is deposited on the insulator. In order to confirm the changes of the surface morphology the atomic force microscopy (AFM) was utilized. The characteristics of the fabricated TFTs are measured to clarify the effects of the surface treatment.

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