• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1141-1144
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• 2011

Range walk has been a major problem in achieving correct Doppler processing. This frequently occurs when range variation is severe just like in a bistatic radar or in high speed target scenario. This paper presents a range walk compensated range-Doppler processing algorithm applicable to the bistatic radar. In order for the compensation, a range-domain interpolation is applied for range compressed signal so that Doppler processing is performed along the evenly time-spaced range bins that contain target returns. Under a bistatic radar scenario, the proposed algorithm including a range domain pulse compression is mathematically described. Finally, the validity of the algorithm is demonstrated by simulation results showing the superiority of a SCDP(Squint Cross-range Doppler Processing) over an uncompensated Doppler processing.

• The Journal of the Acoustical Society of Korea
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• v.26 no.2
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• pp.87-94
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• 2007

In active sonar system, aspect angle and length of a target can be estimated by calculating the cross-correlation between left and right split-beams of a LFM(Linear Frequency Modulated) signal. However, high-resolution performances in bearing and range are required to estimate the information of a remote target. Because a certain higher sampling frequency than the Nyquist sampling frequency is required in this performance, an over-sampling process through interpolation method should be required. However, real-time implementation of split-beam processing with over-sampled split-beam outputs on a COTS(commercial off-the-shelf) DSP platform limits its performance because of given throughput and memory capacity. This paper proposes a cumulative processing algorithm for split-beam processing to solve the problems. The performance of the proposed method was verified through some simulation tests. Also, the proposed method was implemented as a real-time system using an ADSP-TS101.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.16-22
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• 2000

This paper presents a compression algorithm applicable for transmitting a HPO hologram data. The proposed algorithm exploits a modulating function to compress the bandwidth of the hologram pattern, resulting in decimation due to relaxed Nyquist sampling constraints. At the receiver, the compressed data will be interpolated and compensated via being divided by the modulating function. We also present compression rate and analyze the resolution of a reconstructed image and the periodicity of harmonic interferences. Finally, we shows the validity of the proposed algorithm by simulation where a reconstructed image from undersampled data is compared with a reconstructed image obtained through decimatioin by modulating function, interpolation and compensation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.