• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.262-269
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• 2005

Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.37-40
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• 2004

SONOS를 이용한 전하트랩형 플래시 메모리를 통상의 0.35um CMOS 공정을 이용하여 제작하였으며 그 구조는 소스를 공통(CSL. Common Source Line)으로 사용하는 NOR형으로 하였다. 기존의 공정을 그대로 이용하면서 멀티 비트 동작을 통한 실질적 집적도 향상을 얻을 수 있다면 그 의미가 크다고 하겠다. 따라서 본 연구에서는CSL-NOR형 플래시 구조에서 멀티 비트을 구현하기위한 최적의 프로그램/소거/읽기 전압 조건을 구하여 국소적으로 트랩된 전하의 분포를 전하펌핑 방법을 이용하여 조사하였다. 또한 이 방법을 이용하여 멀티 비트 동작 시 문제점으로 제시된 전하의 측면확산을 측정하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1681-1688
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• 2017

In this paper, we implemented a high-speed signal processing hardware system for Color Line Scan Camera using FPGA and Nor-Flash. The existing hardware system mainly processed by high-speed DSP based on software and it was a method of detecting defects mainly by RGB individual logic, however we suggested defect detection hardware using RGB-HSL hardware converter, FIFO, HSL Full-Color Defect Decoder and Image Frame Buffer. The defect detection hardware is composed of hardware look-up table in converting RGB to HSL and 4K HSL Full-Color Defect Decoder with high resolution. In addition, we included an image frame for comprehensive image processing based on two dimensional image by line data accumulation instead of local image processing based on line data. As a result, we can apply the implemented system to the grain sorting machine for the sorting of peanuts effectively.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.21-30
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• 2009

Fusion flash memory such as OneNAND$^{TM}$ is popular as a ubiquitous storage device for embedded systems because it has advantages of NAND and NOR flash memory that it can support large capacity, fast read/write performance and XIP(eXecute-In-Place). Besides, OneNAND$^{TM}$ provides not only advantages of hybrid structure but also multi-block erase function that improves slow erase performance by erasing the multiple blocks simultaneously. But traditional NAND Flash Translation Layer may not fully support it because the garbage collection of traditional FTL only considers a few block as victim block and erases them. In this paper, we propose an Erase Group Flash Translation Layer for improving multi-block erase function. EGFTL uses a superblock scheme for enhancing garbage collection performance and invalid block management to erase multiple blocks simultaneously. Also, it uses clustered hash table to improve the address translation performance of the superblock scheme. The experimental results show that the garbage collection performance of EGFTL is 30% higher than those of traditional FTLs, and the address translation performance of EGFTL is 5% higher than that of Superblock scheme.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.47-57
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• 2008

Recently, energy-efficient NAND Flash memory of large volume is favored as next-generation storage for sensor nodes. So far, most sensor node file systems are based on NOR flash and few file systems are applicable to large NAND flash memory. Although it is required to develop new file systems taking account of the features of NAND flash memory, it is difficult to develop them mainly due to the limit of SRAM memory on sensor nodes. Sensor nodes support SRAM of $4{\sim}10$ KBytes only. In this paper, we designed and implemented a novel file system to support data-centric applications. To do this, we added EEPROM of 1 KBytes to store persistent file description data efficiently and devised a simple wear-leveling method. This reduces the number of page updates, resulting in reduction in energy use and increase in lifetime of sensor nodes.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.357-359
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• 2018

최근 메모리 반도체 시장은 SD(Secure Digital) 메모리 카드, SSD(Solid State Drive)등의 보급률 증가로 메모리 반도체의 시장이 대규모로 증가하고 있다. 메모리 반도체는 개인용 컴퓨터 뿐만 아니라 스마프폰, 테플릿 PC, 교육용 임베디드 보드 등 다양한 산업에서 이용 되고 있다. 또한 메모리 반도체 생산 업체가 대규모로 메모리 반도체 산업에 투자하면서 메모리 반도체 시장은 대규모로 성장되었다. 플래시 메모리는 크게 NAND-Type과 NOR-Type으로 나뉘며 플로팅 게이트 셀의 전압의 따라 SLC(Single Level Cell)과 MLC(Multi Level Cell) 그리고 TLC(Triple Level Cell)로 구분 된다. SLC 및 MLC NAND-Type 플래시 메모리는 많은 연구가 진행되고 이용되고 있지만, TLC NAND-Tpye 플래시 메모리는 많은 연구가 진행되고 있지 않다. 본 논문에서는 기존에 제안된 SLC 및 MLC NAND-Type 플래시 메모리에서 제안된 큐브 패턴을 TLC NAND-Type 플래시 메모리에서 적용 가능한 큐브 패턴 및 알고리즘을 제안한다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.