• 한국진공학회:학술대회논문집
• /
• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
• /
• pp.82-82
• /
• 1999

Ferroelectric materials are characterized by the existence of a spontaneous remnant polarization that can be switched between two stable states by an applied field. This phenomenon is known as ferroelectricity. The ferroelectricity can be utilized for nonvolatile memory application. Up to now 256K FRAM was successfully fabricated and sold in the memory market. This paper will briefly review the current statue of ferroelectric random access memory (FRAM) focusing on recent developments. In addition, the future prospects of FRAM will be addressed.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권2호
• /
• pp.286-291
• /
• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• 한국통신학회논문지
• /
• 제42권5호
• /
• pp.975-981
• /
• 2017

본 논문에서는 WSN 환경에서 플래시 장치를 사용할 때 에너지를 효율적으로 사용하기 위한 방법을 제안한다. 전형적인 플래시 장치는 높은 대기 에너지로 인해 에너지가 제한된 WSN에서 비효율적인 에너지 소모 저장 매체라는 단점을 가지고 있다. 플래시 장치를 WSN 환경에서 에너지 효율적으로 사용하기 가장 쉬운 방법은 유휴 상태일 때 플래시 장치를 끄는 것이다. 이와 관련하여 우리는 비휘발성 및 바이트 주소 지정 기능을 제공하는 새로운 메모리 기술인 NVRAM (Nonvolatile RAM)을 활용하여 높은 대기 에너지 소모 그리고 시작 지연시간을 제거함으로써 간단하지만 이상적인 접근 방식을 현실적으로 제안한다. 특히 NVRAM을 메타 데이터 저장소의 확장으로 사용하여 FTL 메타 데이터 검색 프로세스를 제거하여 앞의 두 가지 장애 요소를 해결 하고자 한다. 실험을 통해 제안하는 방법이 기존 저장장치 비해 약 1.087% 에너지 만을 사용함을 알 수 있었다.

• Transactions on Electrical and Electronic Materials
• /
• 제15권5호
• /
• pp.241-244
• /
• 2014

Charge trap flash memory capacitors incorporating $(HfO_2)_x(Al_2O_3)_{1-x}$ film, as the charge trapping layer, were fabricated. The effects of the charge trapping layer composition on the memory characteristics were investigated. It is found that the memory window and charge retention performance can be improved by adding Al atoms into pure $HfO_2$; further, the memory capacitor with a $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer exhibits optimized memory characteristics even at high temperatures. The results should be attributed to the large band offsets and minimum trap energy levels. Therefore, the $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer may be useful in future nonvolatile flash memory device application.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
• /
• pp.240.2-240.2
• /
• 2013

The device scale of flash memory was confronted with quantum mechanical limitation. The next generation memory device will be required a break-through for the device scaling problem. Especially, graphene is one of important materials to overcome scaling and operation problem for the memory device, because ofthe high carrier mobility, the mechanicalflexibility, the one atomic layer thick and versatile chemistry. We demonstrate the hybrid memory consisted with the metal-oxide quantum dots and the mono-layered graphene which was transferred to $SiO_2$ (5 nm)/Si substrate. The 5-nm thick secondary $SiO_2$ layer was deposited on the mono-layered graphene by using ultra-high vacuum sputtering system which base pressure is about $1{\times}10^{-10}$ Torr. The $In_2O_3$ quantum dots were distributed on the secondary $SiO_2$2 layer after chemical reaction between deposited In layer and polyamic acid layer through soft baking at $125^{\circ}C$ for 30 min and curing process at $400^{\circ}C$ for 1 hr by using the furnace in $N_2$ ambient. The memory devices with the $In_2O_3$ quantum dots on graphene monolayer between $SiO_2$ thin films have demonstrated and evaluated for the application of next generation nonvolatile memory device. We will discuss the electrical properties to understating memory effect related with quantum mechanical transport between the $In_2O_3$ quantum dots and the Fermi level of graphene layer.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
• /
• pp.17-20
• /
• 2001

Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectrics were fabricated, and nitrogen distribution and bonding species which contribute to memory characteristics were analyzed. Also, memory characteristics of devices depending on the anneal temperatures were investigated. The devices were fabricated by retrograde twin well CMOS processes with $0.35{\mu}m$ Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectric were fabricated, and nitrogen distribution and bonding species which contributing memory characteristics were analyzed. Also, memory characteristics of devices according to anneal temperatures were investigated. The devices were fabricated by $0.35{\mu}m$ retrograde twin well CMOS processes. The processes could be simple by in-situ process of nitridation anneal and reoxidation. The nitrogen distribution and bonding state of gate dielectric were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). Nitrogen concentrations are proportional to nitridation anneal temperatures and the more time was required to form the same reoxidized layer thickness. ToF-SIMS results show that SiON species are detected at the initial oxide interface and $Si_{2}NO$ species near the new $Si-SiO_{2}$ interface that formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. These could be said that nitrogen concentration near initial interface is limited to a certain quantity, so excess nitrogen are redistributed near the $Si-SiO_{2}$ interface and contributed to electron trap generation.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2011년도 제40회 동계학술대회 초록집
• /
• pp.118-118
• /
• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2011년도 추계학술발표대회
• /
• pp.20.1-20.1
• /
• 2011

The nano-sized quantum structure has been an attractive candidate for investigations of the fundamental physical properties and potential applications of next-generation electronic devices. Metal nano-particles form deep quantum wells between control and tunnel oxides due to a difference in work functions. The charge storage capacity of nanoparticles has led to their use in the development of nano-floating gate memory (NFGM) devices. When compared with conventional floating gate memory devices, NFGM devices offer a number of advantages that have attracted a great deal of attention: a greater inherent scalability, better endurance, a faster write/erase speed, and more processes that are compatible with conventional silicon processes. To improve the performance of NFGM, metal nanocrystals such as Au, Ag, Ni Pt, and W have been proposed due to superior density, a strong coupling with the conduction channel, a wide range of work function selectivity, and a small energy perturbation. In the present study, bismuth metal nanocrystals were self-assembled within high-k $Bi_2Mg_{2/3}Nb_{4/3}O_7$ (BMN) films grown at room temperature in Ar ambient via radio-frequency magnetron sputtering. The work function of the bismuth metal nanocrystals (4.34 eV) was important for nanocrystal-based nonvolatile memory (NVM) applications. If transparent NFGM devices can be integrated with transparent solar cells, non-volatile memory fields will open a new platform for flexible electron devices.

• 한국전기전자재료학회논문지
• /
• 제24권4호
• /
• pp.325-327
• /
• 2011

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a $SiO_2/Si$ substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 추계학술대회 논문집
• /
• pp.149-150
• /
• 2007

ONO(Oxide-Nitride-Oxide)구조는 기억소자의 전하보유 능력을 향상시키기 위해 도입된 게이트 절연막이다. 본 연구에서는 ELA(Excimer Laser Annealing)방법으로 비정질 실리콘을 결정화 시켜서 그 위에 NVM(Nonvolatile Memory)소자를 만들어 전기적 특성을 측정하여 결과를 나타내었다. 실험 결과 같은 크기의 $V_D$에서 $V_G$를 조절함으로써 $I_D$의 크기를 조절할 수 있었다. $V_G-I_D$ Graph에서는 $I_{on}$과 $I_{off}$, 그리고 Threshold Voltage를 알 수 있었다. $I_{on}/I_{off}$ Ratio는 $10^3-10^4$이다. $V_G-I_D$ Graph에서는 게이트에 인가하는 Bias의 양을 통해서 Threshold Voltage의 크기를 조절할 수 있었다. 이는 Trap되는 Charge의 양을 임의로 조절할 수 있다는 것을 의미하며, 이러한 Programming과 Erasing의 특성을 이용하여 기억소자로서의 역할을 수행하게 된다.