• Title/Summary/Keyword: Nonlinear Capacitance

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Effects of Source and Load Impedance on the Linearity of GaAs MESFET (GaAs MESFET의 소오스 및 부하 임피던스가 선형성에 미치는 영향)

  • 안광호;이승학;정윤하
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.10 no.5
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    • pp.663-671
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    • 1999
  • The linearity of the GaAs FET power amplifier(PA) is greatly influenced by source and load impedance for the FETs. The third order intermodulation products, IM3, from the GaAs FET PA are investigated in relation with source and load impedance. From heuristic as well as analytic point of view, e.g., Volterra series analysis, is employed to analyze the effects of nonlinear circuit elements, gate-source capacitance, $C_{gs}$, and drain-source current, $I_{ds}$. The sweet spots where soure and load impedance produce the least intermodulation products are calculated and compared with the load and source pull data with good agreements. It also shows that source impedance has a greater effect on the intermodulation products than the load impedcnce.

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Influence of post-annealing on DC degradation characteristics in $ZnO-Bi_2O_3$ Varistor ($ZnO-Bi_2O_3$ 계 바리스터에서 후열처리가 DC 열화 특성에 미치는 영향)

  • 소순진;김영진;소병문;박춘배
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.333-336
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    • 1999
  • The relationship between the DC degradation characteristics of the $ZnO-Bi_2O_3$ varistor and post-annealing is investigated in this study. $ZnO-Bi_2O_3$ varistors containing $SiO_2$ range 0.3 mol% were fabricated by standard ceramic techniques. The post- annealing is performed at $550^{\circ}C$ for 0, 1.5 and 5h. A little phase transition is found according to the analysis of X-ray diffraction. DC degradation tests were conducted at $115\pm3^{\circ}C$ for periods up to 22h. Current-voltage analysis was used to determine nonlinear coefficients($\alpha$). Capacitance-voltage analysis enable the donor density($N_d$) and the barrier height($E_B$) to be determined. From above analysis, it is found that the past-annealing for 5h improved degradation characteristics in $ZnO-Bi_2O_3$ with Si additive.

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Parameter Selection of the Saturable Reactor for Removing Ferroresonance of 362kV Gas VT Using EMTP (EMTP를 이용한 362kV Gas VT의 철공진제거를 위한 가포화리엑터의 파라미터 선정)

  • Choi, Jae-Gu;Kim, Ik-Soo;Park, Kyoung-Won;Song, Hee-Suk
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.50 no.4
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    • pp.197-203
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    • 2001
  • Recently, the construction of gas insulated substation(GIS)s has been increased in Korea. But, the whole quantity of the VTs which were used in GIS has been imported. Under the circumstance that $SF_6$ gas power apparatus are being developed up to 800kV rating in Korea, the development of EHV $SF_6$ gas VT is essential for localizing the power apparatus. As for EHV VT, destructive ferroresonance can be generated due to the combination of capacitiances between poles of circuit breaker, ground capacitance of bus and nonlinear excitation property of VT core. But the theoretical analysis about ferroresonance has not been fully achieved in Korea. Therefore, in this paper the authors would like to contribute for localizing EHV $SF_6$ gas VT by developing the diagram of ferroresonance zone according to the parameters of the circuit and the saturable reactor.

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A Study on the Modeling of a High-Voltage IGBT for SPICE Simulations (고전압 IGBT SPICE 시뮬레이션을 위한 모델 연구)

  • Choi, Yoon-Chul;Ko, Woong-Joon;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.12
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    • pp.194-200
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    • 2012
  • In this paper, we proposed a SPICE model of high-voltage insulated gate bipolar transistor(IGBT). The proposed model consists of two sub-devices, a MOSFET and a BJT. Basic I-V characteristics and their temperature dependency were realized by adjusting various parameters of the MOSFET and the BJT. To model nonlinear parasitic capacitances such as a reverse-transfer capacitance, multiple junction diodes, ideal voltage and current amplifiers, a voltage-controlled resistor, and passive devices were added in the model. The accuracy of the proposed model was verified by comparing the simulation results with the experimental results of a 1200V trench gate IGBT.

Sintering and Electrical Properties of Mn-doped ZnO-TeO2 Ceramics (Mn을 첨가한 ZnO-TeO2 세라믹스의 소결과 전기적 특성)

  • Hong, Youn-Woo;Shin, Hyo-Soon;Yeo, Dong-Hun;Kim, Jong-Hee;Kim, Jin-Ho
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.1
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    • pp.22-28
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    • 2009
  • We investigated the sintering and electric properties of ZnO-1.0 at% $TeO_2$ (ZT1) and 1.0 at% Mn-doped ZT1(ZT1M1) system. $TeO_2$ itself melts at $732^{\circ}C$ in air but forms the $ZnTeO_3$ or $Zn_2Te_3O_8$ phase with ZnO as increasing temperature and therefore retards the densification of ZnO to $1000^{\circ}C$. In ZT1M1 system, also, the densification of ZnO was retarded up to $1000^{\circ}C$ and then reached > 90% of theoretical density above $1100^{\circ}C$. It was found that a good varistor characteristics(nonlinear coefficient $a{\sim}60$) were developed in ZT1M1 system sintered at $1100^{\circ}C$ due to Mn which known as improving the nonlinearity of ZnO varistors. The results of C-V characteristics such as barrier height (${\Phi}_b$), donor density ($N_D$), depletion layer (W), and interface state density ($N_t$) in ZT1M1 ceramics were $1.8{\times}10^{17}cm^{-3}$, 1.6 V, 93 nm, and $1.7{\times}10^{12}cm^{-2}$, respectively. Also we measured the resistance and capacitance of grain boundaries with temperature using impedance and electric modulus spectroscopy. It will be discussed about the stability and homogeneity of grain boundaries using distribution parameter ($\alpha$) simulated with the Z(T)"-logf plots.

Effects of CaCO3 on the Defects and Grain Boundary Properties of ZnO-Co3O4-Cr2O3-La2O3 Ceramics (ZnO-Co3O4-Cr2O3-La2O3 세라믹스의 결함과 입계 특성에 미치는 CaCO3의 영향)

  • Hong, Youn-Woo;Ha, Man-Jin;Paik, Jong-Hoo;Cho, Jeong-Ho;Jeong, Young-Hun;Yun, Ji-Sun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.5
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    • pp.307-312
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    • 2018
  • Liquid phases in ZnO varistors cause more complex phase development and microstructure, which makes the control of electrical properties and reliability more difficult. Therefore, we have investigated 2 mol% $CaCO_3$ doped $ZnO-Co_3O_4-Cr_2O_3-La_2O_3$ (ZCCLCa) bulk ceramics as one of the compositions without liquid phase sintering additive. The results were as follows: when $CaCO_3$ is added to ZCCLCa ($644{\Omega}cm$) acting as a simple ohmic resistor, CaO does not form a secondary phase with ZnO but is mostly distributed in the grain boundary and has excellent varistor characteristics (high nonlinear coefficient ${\alpha}=78$, low leakage current of $0.06{\mu}A/cm^2$, and high insulation resistance of $1{\times}10^{11}{\Omega}cm$). The main defects $Zn_i^{{\cdot}{\cdot}}$ (AS: 0.16 eV, IS & MS: 0.20 eV) and $V_o^{\bullet}$ (AS: 0.29 eV, IS & MS: 0.37 eV) were found, and the grain boundaries had 1.1 eV with electrically single grain boundary. The resistance of each defect and grain boundary decreases exponentially with increasing the measurement temperature. However, the capacitance (0.2 nF) of the grain boundary was ~1/10 lower than that of the two defects (~3.8 nF, ~2.2 nF) and showed a tendency to decrease as the measurement temperature increased. Therefore, ZCCLCa varistors have high sintering temperature of $1,200^{\circ}C$ due to lack of liquid phase additives, but excellent varistor characteristics are exhibited, which means ZCCLCa is a good candidate for realizing chip type or disc type commercial varistor products with excellent performance.

Effect of Firing Temperature on Microstructure and the Electrical Properties of a ZnO-based Multilayered Chip Type Varistor(MLV) (소성온도에 따른 ZnO계 적층형 칩 바리스터의 미세구조와 전기적 특성의 변화)

  • Kim, Chul-Hong;Kim, Jin-Ho
    • Journal of the Korean Ceramic Society
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    • v.39 no.3
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    • pp.286-293
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    • 2002
  • Microstructure and the electrical porperties of a ZnO-based multilayered chip-type varistor(abbreviated as MLV) with Ag/Pd(7:3) inner electrode have been studied as a function of firing of temperature. At 1100$^{\circ}$C, inner electrode layers began to show nonuniform thickness and small voids, which resulted in significant disappearance of the electrode pattern and delamination at 1100$^{\circ}$C. MLVs fired at 950$^{\circ}$C showed large degradation in leakage current, probably due to incomplete redistribution of liquid and transition metal elements in pyrochlore phase decomposition. Those fired at 1100$^{\circ}$C and above, on the other hand, revealed poor varistor characteristics and their reproductibility, which are though to stem from the deformation of inner electrode pattern, the reaction between electrode materials and ZnO-based ceramics, and the volatilization of $Bi_2O_3$. Throughout the firing temperature range of 950∼1100$^{\circ}$C, capacitance and leakage current increased while breakdown voltage and peak current decreased with the increase of firing temperature, but nonlinear coefficient and clamping ratio kept almost constant at ∼30 and 1.4, respectively. In particular, those fired between 1000$^{\circ}$C and 1050$^{\circ}$C showed stable varistor characteristics with high reproducibility. It seems that Ag/Pd(7:3) alloy is one of the electrode materials applicable to most ZnO-based MLVs incorporating with $Bi_2O_3$ when cofired up to 1050$^{\circ}$C.

Bias and Gate-Length Dependent Data Extraction of Substrate Circuit Parameters for Deep Submicron MOSFETs (Deep Submicron MOSFET 기판회로 파라미터의 바이어스 및 게이트 길이 종속 데이터 추출)

  • Lee Yongtaek;Choi Munsung;Ku Janam;Lee Seonghearn
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.12
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    • pp.27-34
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    • 2004
  • The study on the RF substrate circuit is necessary to model RF output characteristics of deep submicron MOSFETs below 0.2$\mum$ gate length that have bun commercialized by the recent development of Si submicron process. In this paper, direct extraction methods are developed to apply for a simple substrate resistance model as well as another substrate model with connecting resistance and capacitance in parallel. Using these extraction methods, better agreement with measured Y22-parameter up to 30 GHz is achieved for 0.15$\mum$ CMOS device by using the parallel RC substrate model rather than the simple resistance one, demonstrating the RF accuracy of the parallel model and extraction technique. Using this model, bias and gate length dependent curves of substrate parameters in the RF region are obtained by increasing drain voltage of 0 to 1.2V at deep submicron devices with various gate lengths of 0.11 to 0.5㎛ These new extraction data will greatly contribute to developing a scalable RF nonlinear substrate model.

Porous silicon : a new material for microsensors and microactuators (다공질 실리콘: 새로운 마이크로센서 및 마이크로액추에이터 재료)

  • Min Nam Ki;Chi Woo Lee;Jeong Woo Sik;Kim Dong Il
    • Journal of the Korean Electrochemical Society
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    • v.2 no.1
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    • pp.17-22
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    • 1999
  • Since the use of porous silicon for microsensors and microactuators is in the euly stage of study, only several application devices, such as light-emitting diodes and chemical sensors have so far been demonstrated. In this paper we present an overview of the present status of porous silicon sensors and actuators research with special emphasis on the applications of chemical sensors and optical devices. The capacitive type porous silicon humidity sensors had a nonlinear capacitance-humidity characteristic and a good sensitivity at higher humidity above $40\%RH$. The porous silicon $n^+-p-n^+$ device showed a sharp increase in current when exposed to an ethanol vapor. The $p^+-PSi-n^+$ diode fabricated on porous silicon diaphragm exhibited an optical switching characteristic, opening up its utility as an optical sensor or switch. The photoluminescence (PL) spectrum, taken from porous silicon under 365 nm excitation, had a broad emission, peaked at -610 nm. The electroluminescence(EL) from ITO/PSi/In LED had a broader spectrum with a blue shifted peak at around 535nm than that of the PL.