• Journal of KIISE:Computing Practices and Letters
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• v.14 no.4
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• pp.378-388
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• 2008

Flash memory has been attracting attention as the next mass storage media for mobile computing systems such as notebook computers and UMPC(Ultra Mobile PC)s due to its low power consumption, high shock and vibration resistance, and small size. A storage system with flash memory excels in random read, sequential read, and sequential write. However, it comes short in random write because of flash memory's physical inability to overwrite data, unless first erased. To overcome this shortcoming, we propose an SSD(Solid State Disk) architecture with two novel features. First, we utilize non-volatile FRAM(Ferroelectric RAM) in conjunction with NAND flash memory, and produce a synergy of FRAM's fast access speed and ability to overwrite, and NAND flash memory's low and affordable price. Second, the architecture categorizes host write requests into small random writes and large sequential writes, and processes them with two different buffer management, optimized for each type of write request. This scheme has been implemented into an SSD prototype and evaluated with a standard PC environment benchmark. The result reveals that our architecture outperforms conventional HDD and other commercial SSDs by more than three times in the throughput for random access workloads.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1858-1864
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• 2009

In this paper, we design a non-volatile memory IP, 1-kb one-time programmable (OTP) memory, used for power management ICs. Since a conventional OTP cell uses an isolated NMOS transistor as an antifuse, there is an advantage of it big cell size with the BCD process. We use, therefore, a PMOS transistor as an antifuse in lieu of the isolated NMOS transistor and minimize the cell size by optimizing the size of a OTP cell transistor. And we add an ESD protection circuit to the OTP core circuit to prevent an arbitrary cell from being programmed by a high voltage between the terminals of the PMOS antifuse when the ESD test is done. Furthermore, we propose a method of turning on a PMOS pull-up transistor of high impedance to eliminate a gate coupling noise in reading a non-programmed cell. The layout size of the designed 1-kb PMOS-type antifuse OTP IP with Dongbu's $0.18{\mu}m$ BCD is $129.93{\times}452.26{\mu}m^2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.189.1-189.1
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• 2014

Lead zirconium titanate (PZT) is usually used as bulk and thin films. Due to high flexibility and piezoelectric, ferroelectric and pyroelectric properties, PZT fiber has attracted in a variety of fields such as sensor devices, non-electromechanical systems and non-volatile ferroelectric memory devices. And PZT fiber can be numerously synthesized and almost with the diameter of PZT fiber thicker than $10{\mu}m$. However, the electrospinnig method is cost effective and convenient. PZT obtained by electrospinning methodhas the diameter from sub-micro to nanometer. In this paper, the PZT/PVP nanofibers were synthesized with three precursors, lead nitrate, zirconium ethoxide and titanium isopropoxide. And the PZT nanofibers were fabricated after removal of PVP by annealing process at various temperature. The obtained PZT nanofibers were characterized by means of X-ray photoelectron spectroscopy (XPS) for chemical properties, X-ray diffraction (XRD) for crystallinity and phase, scanning electron microscopy (SEM) for morphologies. The diameter of PZT nanofibers were measured with SEM. From the SEM images, we confirmed that diameter of PZT nanofibers was hundreds of nanometers and decreased with increasing the annealing temperature. When the annealing temperature increased, the crystallinity of PZT nanofibers changed from pyrochlore to perovskite structure.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.4
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• pp.279-285
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• 2000

High quality crystals of $YMnO_3$, which is interested in non-volatile memory device application, were grown by the floating zone method. Optimum condition for powder synthesis was established to be $1200^{\circ}C$ for 10 hrs and optimum condition for sintering of $YMnO_3$feed-rod was established to be $1500^{\circ}C$ for 10hrs respectively. It was found from non-seeded growth experiment that $YMnO_3$crystal was grown preferentially to the [1010] orientation. The $YMnO_3$single crystal, which was grown to the direction of perpendicular to C-axis, was typically 5mm in diameter, 50 mm in length and showed dark-blue color.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.146-152
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• 2011

Thermal stability of $Ge_2Sb_2Te_5$ (GST) and $SiO_2$ doped GST (SGST) films for phase change random access memory applications was investigated by observing the change of surface roughness, layer density and composition of both films after isothermal annealing. After both GST and SGST films were annealed at $325^{\circ}C$ for 20 min, root mean square (RMS) surface roughness of GST was increased from 1.9 to 35.9 nm but that of SGST was almost unchanged. Layer density of GST also steeply decreased from 72.48 to 68.98 $g/cm^2$ and composition was largely varied from Ge : Sb : Te = 22.3 : 22.1 : 55.6 to 24.2 : 22.7 : 53.1, while those of SGST were almost unchanged. It was confirmed that the addition of a small amount of $SiO_2$ into GST film restricted the deterioration of physical and chemical properties of GST film, resulting in the better thermal stability after isothermal annealing.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.15-20
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• 2016

Write amplification is a critical factor that limits the stable performance of flash-based storage systems. To reduce write amplification, this paper presents a new technique that cooperatively manages data in flash storage and nonvolatile memory (NVM). Our scheme basically considers NVM as the cache of flash storage, but allows the original data in flash storage to be invalidated if there is a cached copy in NVM, which can temporarily serve as the original data. This scheme eliminates the copy-out operation for a substantial number of cached data, thereby enhancing garbage collection efficiency. Experimental results show that the proposed scheme reduces the copy-out overhead of garbage collection by 51.4% and decreases the standard deviation of response time by 35.4% on average.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.7
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• pp.394-399
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• 2016

The silicon dioxide ($SiO_2$) was deposited using various gas as oxygen and nitrous oxide ($N_2O$) in nowadays. In order to improve electrical characteristics and the interface state density ($D_{it}$) in low temperature, It was deposited with carbon dioxide ($CO_2$) and silane ($SiH_4$) gas by inductively coupled plasma chemical vapor deposition (ICP-CVD). Each $D_{it}$ of $SiO_2$ using $CO_2$ and $N_2O$ gas was $1.30{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$ and $3.31{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$. It showed $SiO_2$ using $CO_2$ gas was about 2.55 times better than $N_2O$ gas. After 10 years when the thin film was applied to metal/insulator/semiconductor(MIS)-nonvolatile memory(NVM), MIS NVM using $SiO_2$($CO_2$) on tunneling layer had window memory of 2.16 V with 60% retention at bias voltage from +16 V to -19 V. However, MIS NVM applied $SiO_2$($N_2O$) to tunneling layer had 2.48 V with 61% retention at bias voltage from +20 V to -24 V. The results show $SiO_2$ using $CO_2$ decrease the $D_{it}$ and it improves the operating voltage.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.159-160
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• 2012

지난 30년 동안 플래시 메모리의 주류 역할을 하였던 부유 게이트 플래시 메모리는 40 nm 기술 노드 이하에서 셀간 간섭, 터널 산화막의 누설전류 등에 의한 오동작으로 기술적 한계를 맞게 되었다. 또한 기존의 비휘발성 메모리는 동작 시 높은 전압을 요구하므로 전력소비 측면에서도 취약한 단점이 있다. 그러나 이러한 문제점들을 기존의 Si기반의 소자기술이 아닌 새로운 재료나 공정을 통해서 해결하려는 연구가 최근 활발하게 진행되고 있다. 특히, 플래시 메모리의 중요한 구성요소의 하나인 터널 산화막은 메모리 소자의 크기가 줄어듦에 따라서 SiO2단층 구조로서는 7 nm 이하에서 stress induced leakage current (SILC), 직접 터널링 전류의 증가와 같은 많은 문제점들이 발생한다. 한편, 기존의 부유 게이트 타입의 메모리를 대신할 것으로 기대되는 전하 포획형 메모리는 쓰기/지우기 속도를 향상시킬 수 있으며 소자의 축소화에도 셀간 간섭이 일어나지 않으므로 부유 게이트 플래시 메모리를 대체할 수 있는 기술로 주목받고 있다. 특히, TBM (tunnel barrier engineered memory) 소자는 유전율이 큰 절연막을 적층하여 전계에 대한 터널 산화막의 민감도를 증가시키고, 적층된 물리적 두께의 증가에 의해 메모리의 데이터 유지 특성을 크게 개선시킬 수 있는 기술로 관심이 증가하고 있다. 본 연구에서는 Si3N4/Ta2O5를 적층시킨 staggered구조의 tunnel barrier를 제안하였고, Si기판 위에 tunnel layer로 Si3N4를 Low Pressure Chemical Vapor Deposition (LPCVD) 방법과 Ta2O5를 RF Sputtering 방법으로 각각 3/3 nm 증착한 후 e-beam evaporation을 이용하여 게이트 전극으로 Al을 150 nm 증착하여 MIS- capacitor구조의 메모리 소자를 제작하여 동작 특성을 평가하였다. 또한, Si3N4/Ta2O5 staggered tunnel barrier 형성 후의 후속 열처리에 따른 전기적 특성의 개선효과를 확인하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.6
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• pp.297-301
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• 2006

In the present work, we investigate the characteristics of new composition material, chalcogenide $Ge_1Se_1Te_2$ material in order to overcome the problems of conventional PRAM devices. The Tc of $Ge_1Se_1Te_2$ bulk was measured $231.503^{\circ}C$ with DSC analysis. For static DC test mode, at low voltage, two different resistances are observed. depending on the crystalline state of the phase-change resistor. In the first sweep, the as-deposited amorphous $Ge_1Se_1Te_2$ showed very high resistance. However when it reached the threshold voltage(about 11.8 V), the electrical resistance of device was drastically reduced through the formation of an electrically conducting path. The phase transition between the low conductive amorphous state and the high conductive crystal]me state was caused by the set and reset pulses respectively which fed through electrical signal. Set pulse has 4.3 V. 200 ns. then sample resistance is $80\sim100{\Omega}$. Reset pulse has 8.6 V 80 ns, then the sample resistance is $50{\sim}100K{\Omega}$. For such high resistance ratio of $R_{reset}/R_{set}$, we can expect high sensing margin reading the recorded data. We have confirmed that phase change properties of $Ge_1Se_1Te_2$ materials are closely related with the structure through the experiment of self-heating layers.

• Journal of Digital Contents Society
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• v.14 no.2
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• pp.215-222
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• 2013

NAND flash memory-based Solid State Drives (SSD) have lots of merits compared to traditional hard disk drives (HDD). However, random write in SSD is still far slower than sequential read/write and random read. There are two independent approaches to resolve this problem: 1) using part of the flash memory blocks as log blocks, and 2) using internal write buffer (DRAM or Non-Volatile RAM) in SSD. While log blocks are managed by the Flash Translation Layer (FTL), write buffer management has been treated separately from FTL. Write buffer management schemes did not use the exact status of log blocks and log block management schemes in FTL did not consider the behavior of write buffer management scheme. In this paper, we first show that log blocks and write buffer have a tight relationship to each other, which necessitates integrated management of both of them. Since log blocks also can be viewed as another type of write buffer, we can manage both of them as an integrated write buffer. Then we provide three design criteria for the integrated write buffer management scheme which can be very useful to SSD firmware designers.