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A Dual-Mode 2.4-GHz CMOS Transceiver for High-Rate Bluetooth Systems

  • Hyun, Seok-Bong;Tak, Geum-Young;Kim, Sun-Hee;Kim, Byung-Jo;Ko, Jin-Ho;Park, Seong-Su
    • ETRI Journal
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    • v.26 no.3
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    • pp.229-240
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    • 2004
  • This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

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Design of a New CMOS Differential Amplifier Circuit (새로운 구조를 갖는 CMOS 자동증폭회로 설계)

  • 방준호;조성익;김동용;김형갑
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.6
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    • pp.854-862
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    • 1993
  • All of the CMOS analog and analog-digital systems have composed with several basic circuits, and among them, a important block, the amplifier part can affect the system's performance, Therefore, according to the uses in the system, the amplifier circuit have designed as various architectures (high-gain, low-noise, high-speed circuit, etc...). In this paper, we have proposed a new CMOS differential amplifier circuit. This circuit is differential to single ended input stage comprised of CMOS complementary gain circuits having internally biasing configurations. These architectures can be achieved the high gain and reduced the transistors for biasing. As a results of SPICE simulation with the standard $1.5{\mu}m$ processing parameter, the gain of the proposed circuit have a doubly value of the typical circuit's while maintaining other characteristics(phase margin, offset, etc...). And the proposed circuit is applicated in a simple CMOS comparator which has the settling time in 7nsec(CL=1pF) and the igh output swing $({\pm}4.5V)$.

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Low-Power ECG Detector and ADC for Implantable Cardiac Pacemakers (이식형 심장 박동 조율기를 위한 저전력 심전도 검출기와 아날로그-디지털 변환기)

  • Min, Young-Jae;Kim, Tae-Geun;Kim, Soo-Won
    • Journal of IKEEE
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    • v.13 no.1
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    • pp.77-86
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    • 2009
  • A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

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The Reliability Design Method According to the Experimental Study of Components and Materials of Railway Rail Fastening System (철도용 레일체결장치 부품.소재의 실험적 연구를 통한 신뢰성 설계 방안)

  • Kim, Hyo-San;Park, Joon-Hyung;Kim, Myung-Ryule;Park, Kwang-Hwa;Lee, Dal-Jae
    • Proceedings of the KSR Conference
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    • 2011.10a
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    • pp.2090-2100
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    • 2011
  • Railway rail fastening system is the critical device which gives big influences to not only the vehicle driving stability and the orbit's structural stability against the impulsive load, but also the noise vibration and the ride comfort. As a part of the low-carbon green growth, the importance of the railroad industry is getting highlights on its excellent energy-efficiency and eco-friendliness. However, so far the Korea's domestic rail fastening system technology is not so good and the technical reliance to abroad is very heavy. In this study, we conducted comparative analysis on the rail fastening system with new and used one of the same type. And those systems are imported by Seoul Metro and are being used by it. With this basis, we developed the components and the materials and then, established the durability assessment methods appropriate to the Korean domestic circumstances. And through the reliability qualification test on the 7 parts of the rail fastening system, we've improved the reliability and guaranteed the 15 years of service lifetime. ($B_{10}Life15$) Establishment and standardization of Reliability Standard on the parts of the rail fastening system such as anti-vibration pads, guide-plate, screw spike made it possible to perform the internationally fair assessment. And it is thought that we can satisfy the manufactures' and consumers' needs of cost-cutting and qualification security by shortening of assessment period on rail fastening system.

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Study on the Broadband RF Front-End Architecture (광대역 RF 전단부 구조에 관한 연구)

  • Go, Min-Ho;Pyo, Seung-Chul;Park, Hyo-Dal
    • The Journal of the Korea institute of electronic communication sciences
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    • v.4 no.3
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    • pp.183-189
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    • 2009
  • In this paper, we propose RF front-end architecture using hybrid conversion method to receive broadband signal. The validity is verified by design, fabrication and experiment. The proposed RF front-end architecture due to up-conversion block improves the deficiency of performance deterioration to be generated through harmonic signal and image signal conversion in the conventional RF front-end, and improves the deficiency of the complexity that is from to adopt a multiple local oscillators for the generation of wideband LO signal in the conventional RF front-end by applying the principle that tuning bandwidth is multiplied at sub-harmonic mixer. Manufactured circuits satisfy the deduced design specification and target standard with gain above 80 dB, noise figure below 6.0 dB and IIP3 performance above -5.0 dBm for the condition of the minimum gain in RF front-end.

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Risk Factors Related to Photo Couplers(P/C) for Signal Transmission by Electronic Devices (전자기기의 신호전송을 위한 Photo Couplers(P/C) 의 위험 요소 발굴)

  • Park, Hyung-Ki;Choi, Chung-Seog
    • Journal of the Korean Society of Safety
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    • v.28 no.2
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    • pp.26-30
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    • 2013
  • The purpose of this study is to find risk factors by analyzing the operation principle of a photo coupler (P/C) used to remove the noise of electronic devices and establish a base for the performance improvement of developed products. It was found from the P/C circuit analysis of normal products that they were equipped with an electrolytic condenser of $0.1{\mu}F$ to smooth system signals. Due to the epoxy resin packing the external part of the P/C, this study experienced a limit to visually examine the damage to it. It could be seen from the analysis of electric characteristics of the P/C that the forward voltage ($V_f$) and reverse current ($I_r$) were 1.3 V and 10 uA, respectively. In addition, it is required that the breakdown voltage (VCE) between the collector (C) and emitter (E) be maintained at less than 35 V. The and of the damaged product #1 were comparatively good. However, the measurement of was 100.0 uA. From this, it is thought that a short circuit occurred to the internal circuit. Moreover, from the fact that the of the damaged product #2 was open circuit and the measurement of was 0.0 uA, it is thought that the collector and emitter was separated or insulation resistance was significantly high. Furthermore, from the fact that the of the damaged product #3 was open circuit and the measurement of was 0.0 uA, it is thought that the space between the collector (C) and emitter (E) failed to meet the design standard or that they were separated. Therefore, it is thought that fabricating the P/C by increasing the reverse current 10 mA to 50 mA will prevent its malfunction.

A Study on University Dining Facilities with the Application of Space Marketing Factors - Focused on H university in Seoul - (스페이스 마케팅 요인을 적용한 대학 학생식당에 관한 연구 - 서울 H대학을 중심으로 -)

  • Lee, Mi-Na;Byun, Dae-Joong
    • Korean Institute of Interior Design Journal
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    • v.21 no.4
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    • pp.200-210
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    • 2012
  • The objective of this study is to activate dining facilities by integrating the factors of space marketing. In this study, It extracts the factors of space marketing applied in the real space on the basis of precedent studies. The selection standard of precedent studies focused on the planning and strategy of space marketing conducted after 2000, and 28 factors in total 16 precedent studies were extracted. We extracted only the factors of space marketing which is applicable to dining facilities by merging and reestablishing them. The extracted 12 factors included. In this way, we conducted a survey on the factors of space marketing as well as utilization and satisfaction considered to be needed for the activation of dining facilities based on H university dining facility in Seoul. Accordingly, I collected a total of 215 copies and analyzed them by SPSS program. According to the result, it indicated that there were many students who primarily used the outside dining facilities rather than university dining facilities regarding the utilization of university dining facilities, and unsatisfactory factors included the design and size of the entrance, quality of the serving space, quality and noise of the dining space, other facilities, size and quality of the rest space and drinking fountain, snack bar, and cafe regarding the satisfaction of each space. It also indicated that the factors which influent the image of university dinning facilities the most included the marketing factors considered to activate university dining facilities such as spatial factors, sensuous factors, and environment friendly factors in order. Therefore, we can consider the interacting operation system that students primarily decorate, improve and use the spaces of the outside dining facilities and other university dining facilities. In conclusion, it's need to consider activating university dining facilities which have been responsible for only basic parts by integrating the marketing factors in common with the outside dining facilities.

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Change of Cerebrovascular Reactivity by Prandial State in Women with Migraine without Aura: Transcranial Doppler Ultrasonography (TCD) with Breath-Holding Method (두개경유도플러초음파를 이용한 성인 여성 무조짐편두통 환자의 식사 상태에 따른 뇌혈관반응성 변화)

  • Park, Jeong-Ho;Park, Sun-Ah;Lee, Tae-Kyeong;Sung, Ki-Bum
    • Annals of Clinical Neurophysiology
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    • v.14 no.1
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    • pp.20-24
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    • 2012
  • Background: Migraine patients can be sensitive to external or internal stimuli, such as light, noise, or hormonal changes. Using transcranial Doppler ultrasonography (TCD) with breath-holding method, we evaluated the changes of cerebrovascular reactivity (CVR) to hypercapnia in women with migraine without aura between fasting and postprandial period. Methods: Twelve women with migraine without aura and the same number of age and sex-matched healthy controls with no significant history of headache participated in this study. Using TCD examinations, we studied mean flow velocity in middle cerebral artery with better temporal window. Each subject was examined consecutively before and after a standard meal, together with serum glucose level and blood pressure. CVR was evaluated with breath-holding index (BHI). Results: Postprandial-BHI (mean+SD) was significantly higher than fasting-BHI (mean+SD) in patients group but not in controls (in patient group; postprandial-BHI=1.38, fasting-BHI=1.08, in control group; postprandial-BHI=1.25, fasting-BHI=1.18, P=0.021 and 0.239, respectively). After meal, serum glucose level was significantly enhanced but blood pressure was not in both groups. Serum glucose level of patients showed a tendency of mild positive correlation with BHIs (${\gamma}$=0.448, P=0.032). Conclusions: Although exact mechanisms are unclear, cerebrovascular reactivity of some women with migraine without aura may be influenced by prandial state.

A Study on the Induced Voltages on Subscriber Telecommunication Lines from High-Speed Electrified Railway Line (고속전철에 의한 통신선로 전력유도 현상에 관한 고찰)

  • Oh, Ho-Seok;Kang, Seong-Yong;Yun, Ju-Yeong;Kim, Hak-Chul;Choi, Kyung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.10
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    • pp.71-79
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    • 2008
  • This paper analyzed the voltage induction phenomena on the telecommunication lines by electromagnetic coupling from high-speed A.C. electrified railway. The induced common mode voltages and the induced differential mode voltage on the telecommunication line was measured by notified standard method in the regulation of Korea. The test lines consist of 2 separated lines of 20 m and 300 m in influence distance each for comparison, with 2km inducing length. The analysis is made on the induced voltages from the different influence distances and the different earthing points, and also on the waveform and spectrum distributions. It is proved that the induction is arisen so good and the measured values are fair enough against noise such as the earth voltage differencing, and the current measuring scheme is also rightful.

A Feedback Wideband CMOS LNA Employing Active Inductor-Based Bandwidth Extension Technique

  • Choi, Jaeyoung;Kim, Sanggil;Im, Donggu
    • Smart Media Journal
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    • v.4 no.2
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    • pp.55-61
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    • 2015
  • A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.