• Journal of Surface Science and Engineering
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• v.48 no.1
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• pp.23-26
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• 2015

What causes the transformation of a solar cell is the behavior difference of thermal expansion occurred between the substrate and the layer of semiconductor used in the solar cell. Therefore, the substrate has to possess a behavior of thermal expansion that is similar with that of semiconductor layer. This study employed electroforming to manufacture Fe-Ni alloy materials of different compositions. To verify the result from a finite element analysis, a two-dimensional Mo substrate was calculated and its verification experiment was conducted. The absolute values from the finite element analysis of Mo/substrate structure and its verification experiment showed a difference. However, the size of residual stress of individual substrate compositions had a similar tendency. Two-dimensional CIGS/Mo/$SiO_2$/substrate was modeled. Looking into the residual stress of CIGS layer occurred while the temperature declined from $550^{\circ}C$ to room temperature, the smallest residual stress was found with the use of Fe-52 wt%Ni substrate material.

• Proceedings of the Korean Ceranic Society Conference
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• 2002.10a
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• pp.32.2-32
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• 2002

• Korean Journal of Materials Research
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• v.20 no.5
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• pp.241-245
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• 2010

One of the weak points of the Cr-doped SZO is that until now, it has only been fabricated on perovskite substrates, whereas NiO-ReRAM devices have already been deposited on Si substrates. The fabrication of RAM devices on Si substrates is important for commercialization because conventional electronics are based mainly on silicon materials. Cr-doped ReRAM will find a wide range of applications in embedded systems or conventional memory device manufacturing processes if it can be fabricated on Si substrates. For application of the commercial memory device, Cr-doped $SrZrO_3$ perovskite thin films were deposited on a $SrRuO_3$ bottom electrode/Si(100)substrate using pulsed laser deposition. XRD peaks corresponding to the (112), (004) and (132) planes of both the SZO and SRO were observed with the highest intensity along the (112) direction. The positions of the SZO grains matched those of the SRO grains. A well-controlled interface between the $SrZrO_3$:Cr perovskite and the $SrRuO_3$ bottom electrode were fabricated, so that good resistive switching behavior was observed with an on/off ratio higher than $10^2$. A pulse test showed the switching behavior of the Pt/$SrZrO_3:Cr/SrRuO^3$ device under a pulse of 10 kHz for $10^4$ cycles. The resistive switching memory devices made of the Cr-doped $SrZrO_3$ thin films deposited on Si substrates are expected to be more compatible with conventional Si-based electronics.

• Journal of the Korean Ceramic Society
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• v.43 no.2 s.285
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• pp.85-91
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• 2006

Electron Beam Physical Vapor Deposition (EB-PVD) was applied to fabricate a thin film YSZ electrolyte with large area on the porous NiO-YSZ anode substrate. Microstructural and thermal stability of the as-deposited electrolyte film was investigated via SEM and XRD analysis. In order to obtain an optimized YSZ film with high stability, both temperature and surface roughness of substrate were varied. A structurally homogeneous YSZ film with large area of $12\times12\;cm^2$ and high thermal stability up to $900^{\circ}C$ was fabricated at the substrate temperature of $T_s/T_m$ higher than 0.4. The smoother surface was proved to give the better film quality. Precise control of heating and cooling rate of the anode substrate was necessary to obtain a very dense YSZ electrolyte with high thermal stability, which affords to survive after post heat treatment for fabrication a cathode layer on it as well as after long time operation of solid oxide fuel cell at high temperature.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.58.1-58.1
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• 2010

We have developed a novel crystallization process, where the crystallization temperature is lowered compared to the conventional RTA process and the metal contamination is lowered compared to the conventional VIC process. A very-thin a-Si film was deposited and crystallized at $550^{\circ}C$ for 3 h by the VIC process and then a thick a-Si film was deposited and crystallized by the RTA process at $680^{\circ}C$ for 5 min using the VIC poly-Si layer as a crystallization seed layer. The RTA crystallized temperature could be lowered up to $50^{\circ}C$, compared to RTA process alone. The poly-Si film appeared a needle-like growth front and relatively well-arranged (111) orientation. In addition, the Ni concentration in the poly-Si film was lowered to $3{\times}10^{17}\;cm^{-3}$ and that at the poly-Si/$SiO_2$ interface was lowered to $5{\times}10^{19}\;cm^{-3}$. The reduction in metal contamination could be greatly helpful to achieve a low leakage current in poly-Si TFT, which is the critical parameter for commercialization of AMOLED.

• Transactions on Electrical and Electronic Materials
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• v.13 no.5
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• pp.215-220
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• 2012

Miniature ultrasonic and tactile sensors on Si substrate have been proposed, fabricated and characterized to detect objects for a dexterous robot. The ultrasonic sensor consists of piezoelectric PZT thin film on a Pt/Ti/$SiO_2$ and/or Si diaphragm fabricated using a micromachining technique; the ultrasonic sensor detects the piezoelectric voltage as an ultrasonic wave. The sensitivity has been enhanced by improving the device structure, and the resonant frequency in the array sensor has been equalized. Position detection has been carried out by using a sensor array with high sensitivity and uniform resonant frequency. The tactile sensor consists of four or three warped cantilevers which have NiCr or $Si:B^+$ piezoresistive layer for stress detection. Normal and shear stresses can be estimated by calculation using resistance changes of the piezoresitive layers on the cantilevers. Gripping state has been identified by using the tactile sensor which is installed on finger of a robot hand, and friction of objects has been measured by slipping the sensor.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.873-875
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• 1999

We have fabricated good quality superconducting $YBa_{2}Cu_{3}O_{7-\delta}$ thin films on Hastelloy(Ni-Cr-Mo alloys) metallic substrate with $CeO_2$ and $BaTiO_3$ buffer layers in-situ by pulsed laser deposition in a multi-target processing chamber. We have chosen $CeO_2$ as a buffer layer which has cubic structure of $5.41{\AA}$ lattice parameter and only 0.2% of lattice mismatch with YBCO. $CeO_2$ layer may be helpful for power transmission due to its conducting property. In order to enhance the crystallization of YBCO films on metallic substrates. we deposited $CeO_2$ and $BaTiO_3$ buffer layers at various temperatures. The YBCO superconducting tape fabricated with $BaTiO_3$ and $CeO_2$ buffer layers shows 85K of transition temperature and about $8.4{\times}10^4A/cm^2$ of critical current density at 77K.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.05a
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• pp.45-46
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• 2015

Se 원소가 포함된 $CuIn_xGa_{1-x}Se_2$(CIGS) 단일 스퍼터링 타겟을 이용하여 후처리 공정없이 단일 스퍼터링 공정만으로 CIGS 흡수층 박막을 증착하여 소자 특성을 확인하였다. 단일 CIGS 흡수층 공정이 적용된 CIGS 박막태양전지 소자(유리기판/Mo/단일 CIGS 흡수층 박막/CdS/i-ZnO/Al-doped ZnO/Ni-Al grid)에서 10.0%의 태양광 변환 효을을 달성하였으며, 이는 기존의 복잡한 공정구조를 해결하여 대면적 양산화 CIGS 제조 공정에도 적용할 수 있음을 확인하였다.