• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.27-33
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• 2008

With increasing use of portable appliances such as PDA and cellular phone, changing environment of applications requires higher solder joint reliability. The ENIG (Electroless Nickel Immersion Gold) process has been widely used for fine pitch SMT (Surface Mount Technology) and BGA (Ball Grid Array) packaged devices due to its benefits including excellent solderability, high uniformity and substantial legibility throughout the packaging process. Its brittle fracture of solder, however, has received increasingly attentions. It was Down that fracture brittleness is mainly related with black pad resulting from galvanic nickel corrosion and P-enriched layer formation between the IMC (Intermetallic Compounds) and electroless nickel layer. Theoretically, smooth electroless Ni layer was blown to have a advantages in minimizing the black pad phenomenon by uniform solution exchange during immersion gold plating. Nevertheless, how to control the surface morphology of electroless Ni layer has been hardly blown. This study investigates an effect of surface morphology of Cu underlayer on surface morphology of electroless Ni layer. To obtain various kinds of surface morphology of Cu layer, two types of Cu etching chemical and a number of Cu etching treatment were applied.

• Membrane and Water Treatment
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• v.11 no.4
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• pp.283-294
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• 2020

This work aims at studying the feasibility of continuous removal of mixed heavy metal ions from simulated zinc plating wastewaters by coupling a microbial fuel cell and a microbial electrolysis cell in batch and continuous modes. The discharging voltage of MFC increased initially from 0.4621 ± 0.0005 V to 0.4864 ± 0.0006 V as the initial concentration of Cr⁶⁺ increased from 10 ppm to 60 ppm. Almost complete removal of Cr⁶⁺ and low removal of Cu²⁺ occurred in MFC of the MFC-MEC-coupled system after 8 hours under the batch mode; removal efficiencies (REs) of Cr⁶⁺ and Cu²⁺ were 99.76% and 30.49%. After the same reaction time, REs of nickel and zinc ions were 55.15% and 76.21% in its MEC. Cu²⁺, Ni²⁺, and Zn²⁺ removal efficiencies of 54.98%, 30.63%, 55.04%, and 75.35% were achieved in the effluent within optimum HRT of 2 hours under the continuous mode. The incomplete removal of Cu²⁺, Ni²⁺ and Zn²⁺ ions in the effluent was due to the fact that the Cr⁶⁺ was almost completely consumed at the end of MFC reaction. After HRT of 12 hours, at the different sampling locations, Cr⁶⁺ and Cu²⁺ removal efficiencies in the cathodic chamber of MFC were 89.95% and 34.69%, respectively. 94.58%, 33.95%, 56.57%, and 75.76% were achieved for Cr⁶⁺, Cu²⁺, Ni²⁺ and Zn²⁺ in the cathodic chamber of MEC. It can be concluded that those metal ions can be removed completely by repeatedly passing high concentration of Cr⁶⁺ through the cathode chamber of MFC of the MFC-MEC-coupled system.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.110-113
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• 2003

여러가지 Sn-Ag-Cu 솔더조성과 솔더링 후의 냉각속도에 따라 솔더링 접합부에서의 계면 미세조직의 다양한 변화를 관찰해 보았다. 현재까지 Sn-Ag-Cu 3원계 공정점에 대한 정확한 연구가 미흡하고, 상용으로 제품화되고 있는 Sn-Ag-Cu 합금계는 3원계 공정조성에서 약간 벗어난 조성들을 선택하고 있다고 할 수 있다. 따라서, 본 연구에서 사용한 Sn-Ag-Cu 합금 조성은 Sn-3.5Ag, Sn-3Ag-0.7Cu, Sn-3Ag-1.5Cu, Sn-3.7Ag-0.9Cu, Sn-6Ag-0.5Cu로 선택하였으며, 각 조성에서 Lap Shear Joint를 제조하였다. 사용한 Solder pad는 Cu pad와 Cu pad 위에 Au/Ni를 plating한 것을 이용하였다. 리플로우 솔더링 조건은 $250^{\circ}C$ 이상의 온도에서 60초 실시하였으며, 리플로우 솔더링 후의 냉각속도를 달리하여 냉각시켰다. 솔더링 후의 냉각속도가 느려질수록 계면 금속간화합물(IMC)의 두께가 더욱 증가하며, 조대화되었다. 또한 솔더 조성의 영향에서 Cu와 Ag의 함량이 높을수록 계면 IMC의 두께가 증가되었으며, 이는 솔더내부에 형성된 IMC 입자들이 조대화되어 계면 IMC층에 결합되어 나타났기 때문이다.

• Journal of the Korean institute of surface engineering
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• v.45 no.6
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• pp.248-256
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• 2012

A Pd-based hydrogen membranes for hydrogen purification and separation need high hydrogen perm-selectivity. The surface roughness of the support is important to coat the pinholes free and thin-film membrane over it. Also, The pinholes drastically decreased the hydrogen perm-selectivity of the Pd-based composite membrane. In order to remove the pinholes, we introduced various surface pre-treatment such as alumina powder packing, nickel electro-plating and micro-polishing pre-treatment. Especially, the micro-polishing pretreatment was very effective in roughness leveling off the surface of the porous nickel support, and it almost completely plugged the pores. Fine Ni particles filled surface pinholes with could form open structure at the interface of Pd alloy coating and Ni support by their diffusion to the membrane and resintering. In this study, a $4{\mu}m$ surface pore-free Pd-Cu-Ni ternary alloy membrane on a porous nickel substrate was successfully prepared by micro-polishing, high temperature sputtering and Cu-reflow process. And $H_2$ permeation and $N_2$ leak tests showed that the Pd-Cu-Ni ternary alloy hydrogen membrane achieved both high permeability of $13.2ml{\cdot}cm^{-2}{\cdot}min^{-1}{\cdot}atm^{-1}$ permation flux and infinite selectivity.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.11-16
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• 2004

Electronic devices are getting smaller due to integration of electronic chip, and heat generated in electronic devices can cause loss of performance and/or reliability of the devices. In this research, metals such as gold, nickel and copper are plated onto a porous membrane by electroless plating method to make an efficient micro-heatsinks. Electroless plating includes sensitization and activation steps in pre-treatment steps. A polycarbonate(PC) membrane was sensitizied, activated and deposited in each metal solution for plating. Among manufactured microfibrils, heat transfer and radiation properties of Ni-microfibril with high surface area were more effective than those of $Au^-$ and Cu-microfibril.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.204.1-204.1
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• 2014

스마트폰과 같은 통신기기 및 각종 전자제품에 있어 크기의 축소와 간소화 추세에 따라 인쇄회로기판(PCB)의 초미세회로설계 기술이 요구됨에 따라, 인쇄회로기판과 첨단 전자부품 사이의 접합 신뢰성을 향상시키기 위해 무전해 니켈 도금이 널리 사용되고 있다. 일반적으로, 무전해 Ni도금은 강산, 강염기성 용액을 이용하여 수행되고 있다. 따라서, 공정과정 중에 기판의 손상을 초래하기도 할뿐만 아니라, 환경적으로도 문제시 되고 있다. 본 연구에서는 친환경적 도금공정의 개발을 위해 중성에서 N-(B)무전해 도금을 시행하였다. 중성의 무전해 도금공정은 어떠한 기판을 사용하여도 기판의 손상없이 도금이 가능하다는 장점을 가지고 있고, Boron(B)은 Ni을 비정질화 시키는 물질로 알려져 있다. B가 첨가된 무전해 Ni도금 박막에 있어 B의 영향을 알아보기 위하여 중성조건에서 B를 포함한 DMAB의 첨가량을 조절하였다. Ni-(B) 무전해 도금 시 도금조의 온도는 $40^{\circ}C$로 하였고, 무전해 도금액의 pH는 7(중성)로 유지하였다. Cu Foil기판을 사용하여 DMAB의 양에 따라 성장된 Ni-B무전해 도금 박막의 특성을 분석하기 위해 X-ray Diffraction (XRD), Field Emission Scanning Electron Microscope (FE-SEM), Optical microscope (OM), X-ray Photoelectron Spectroscopy (XPS), X-ray Absorption Spectroscopy (XAS)을 이용하였다.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.372-376
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• 1999

The deposited Cu film on the ferrite magnet was more deposited comparing with that on the plastic magnet. The Cu film became thicker on the S pole comparing with that on the N pole in the both of magnets. The thickness and texture coefficient of deposited copper film affected with direction of line of magnetic force. The difference of pole had little or no effect to the texture coefficient of deposited nickel film. The reaction rate on ferrite magnet and S pole was faster comparing with that on plastic magnet and N pole.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.145-149
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• 1995

The metallization is the key to determining cell costs, call performance, and cell and system reliabiltiy. The Burled Contact Solar Cell (BCSC) was specifical1y desinged to be compatible tilth low cost, mass production techniques and avoid the conventional metallization problem. By using electroless plating trchniqeu, we performed this metallization inexpensively and reliabley, This paper presents the details of the optimization procedure of metallization schemes on laser grooved cell surface Commercially available Ni ,Cu, and Ag plating solutions were applied for the cell metallization. The application of those solutions on the buried contact front metalization has resulted in an cell efficiency of 18.5% The cell parameters are an open circuit voltage of 651 mV, short circuit current density of 38.6 mA/$\textrm{cm}^2$, and fill factor of 73.5%.

• Journal of the Korean institute of surface engineering
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• v.50 no.5
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• pp.373-379
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• 2017

Dry processes like evaporation and sputtering in vacuum chamber are difficult to make a uniform, large area and high quality film on thin PET substrate because of PET degradation and bad adhesion. On the other hand, wet processes like electro or electroless plating have complex processes and require high environmental cost. In this study, we successfully prepared $2{\mu}m$ Zn/Cu/Ni multilayers coated on $12{\mu}m$ polyethylene terephthalate (PET) substrate by using dry-wet mixing processes. Their surface electric resistances were evaluated around $0.2{\Omega}$ by using 4 probe measurements. Furthermore, their corrosion resistance also evaluated by natural potential test and compared with other wet, dry and mixing process samples.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.