• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.4
• /
• pp.155-165
• /
• 1994

An analog neural network circuit of rhigh density integration is introduced. It's prototype chip is designed in 3 by 3 mm2 die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by cascading several chips. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.11
• /
• pp.66-73
• /
• 1993

This paper presents an analog circuit implementation and experimental resuls of the Hopfield type neural network. The proposed architecture enables the reconfiguration betwewn feedback and feedforward networks and employs new circuit designs for the weight supply and storage, analog multilier, nd current-voltage converter, in order to achieve area efficiency as well as function al versatility. The layout design of the eight-neuron neural network is tested as an associative memory to verify its applicability to real world.

• Journal of information and communication convergence engineering
• /
• v.10 no.2
• /
• pp.194-199
• /
• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• Journal of Biomedical Engineering Research
• /
• v.17 no.1
• /
• pp.79-84
• /
• 1996

A number of experimental evidences suggest that the rnun ventrolateral medulla(RVLM) is the final common pathway in the regulation of arterial blood pressure. A Voup of neurons in the RVLM, called the cardiovascular neurons (UN), show spontaneous activity temporally synchronized with the periodic cardiac cycle. These neurons affect the sympathetic nerve discharge(SND), thus are believed to be responsible for blood pressure control. The present experiment identified 98 UVNs in 42 cats based on the temporal relationships between each neuron's activity with both the cardiac cycle and SWD. In 20 UWL changes of spontaneous firing rate(FR) during the somatosympathetic reflex(SSR) were studied Five different firing patterns were observed during the pressor and depressor responses of SSR, implying that they form an interconnected neuronal circuit interacting with one another to generate efferent signals for blood pressure regulation. In the following companion paper, the firing patterns of CVN are analyzed to develop a minimal neuronal circuit model explaining the present experimental outcome.

• Journal of Biomedical Engineering Research
• /
• v.17 no.1
• /
• pp.71-80
• /
• 1996

A number of experimental evidences suggest that the rnun ventrolateral medulla(RVLM) is the final common pathway in the regulation of arterial blood pressure. A Voup of neurons in the RVLM, called the cardiovascular neurons (UN), show spontaneous activity temporally synchronized with the periodic cardiac cycle. These neurons affect the sympathetic nerve discharge(SND), thus are believed to be responsible for blood pressure control. The present experiment identified 98 UVNs in 42 cats based on the temporal relationships between each neuron's activity with both the cardiac cycle and SWD. In 20 UWL changes of spontaneous firing rate(FR) during the somatosympathetic reflex(SSR) were studied Five different firing patterns were observed during the pressor and depressor responses of SSR, implying that they form an interconnected neuronal circuit interacting with one another to generate efferent signals for blood pressure regulation. In the following companion paper, the firing patterns of CVN are analyzed to develop a minimal neuronal circuit model explaining the present experimental outcome.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.37 no.5
• /
• pp.45-53
• /
• 2000

This paper presents an analysis of the dynamical behavor in the chaotic neuron fabricated using 0.8${\mu}{\textrm}{m}$ single poly CMOS technology. An approximated empirical equation models for the sigmoid output function and chaos generative block of the chaotic neuron are extracted from the measurement data. Then the dynamical responses of the chaotic neuron such as biurcation diagram, frequency responses, Lyapunov exponent, and average firing rate are calculated with numerical analysis. In addition, we construct the chaotic neural networks which are composed of two chaotic neurons with four synapses and obtain bifurcation diagram according to synaptic weight variation. And results of experiments in the single chaotic neuron and chaotic neural networks by two neurons with the $\pm$2.5V power supply and sampling clock frequency of 10KHz are shown and compared with the simulated results.

• Applied Microscopy
• /
• v.46 no.4
• /
• pp.171-175
• /
• 2016

A distinctive neuronal network in the brain is believed to make us unique individuals. Electron microscopy is a valuable tool for examining ultrastructural characteristics of neurons, synapses, and subcellular organelles. A recent technological breakthrough in volume electron microscopy allows large-scale circuit reconstruction of the nervous system with unprecedented detail. Serial-section electron microscopy-previously the domain of specialists-became automated with the advent of innovative systems such as the focused ion beam and serial block-face scanning electron microscopes and the automated tape-collecting ultramicrotome. Further advances in microscopic design and instrumentation are also available, which allow the reconstruction of unprecedentedly large volumes of brain tissue at high speed. The recent introduction of correlative light and electron microscopy will help to identify specific neural circuits associated with behavioral characteristics and revolutionize our understanding of how the brain works.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.11 no.4
• /
• pp.63-69
• /
• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.598-602
• /
• 2003

In this paper, we propose the method to control the position of LDM(Linear DC Motor) using vision system. The proposed method is composed of a vision system for position detecting, and main computer calculates PID control output which is deliver to 8051 actuator circuit in serial communication. To confirm the usefulness of the proposed method, we experimented about position control of a small size LDM using CCD camera which has a performance 30frames/sec as vision system.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1188-1191
• /
• 2002

A number of studies have recently been published concerning neuron models and asynchronous neural networks. In the case of large-scale neural networks having neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, because of the limitation of the computational power, In this paper, we discuss the circuit structure of a synaptic section model having the spatio-temporal summation of inputs and utilizing CMOS processing.