• Title/Summary/Keyword: Network-On-Chip

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범용 신경망 연산기(ERNIE)를 위한 학습 모듈 설계 (Design of Learning Module for ERNIE(ERNIE : Expansible & Reconfigurable Neuro Informatics Engine))

  • 정제교;위재우;동성수;이종호
    • 대한전기학회논문지:시스템및제어부문D
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    • 제53권12호
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    • pp.804-810
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    • 2004
  • There are two important things for the general purpose neural network processor. The first is a capability to build various structures of neural network, and the second is to be able to support suitable learning method for that neural network. Some way to process various learning algorithms is required for on-chip learning, because the more neural network types are to be handled, the more learning methods need to be built into. In this paper, an improved hardware structure is proposed to compute various kinds of learning algorithms flexibly. The hardware structure is based on the existing modular neural network structure. It doesn't need to add a new circuit or a new program for the learning process. It is shown that rearrangements of the existing processing elements can produce several neural network learning modules. The performance and utilization of this module are analyzed by comparing with other neural network chips.

내장형 네트워크 프로세서의 설계 및 구현 (Design and implementation of an Embedded Network Processor)

  • 정진우;김성철
    • 한국정보통신학회논문지
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    • 제9권6호
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    • pp.1211-1217
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    • 2005
  • Embedded system은 소수의 System-On-Chip (SOC)으로 대부분의 기능이 구현되어지는 추세이며, 이러한 SOC의 구조는 대체로 RISC 기반의 내장 마이크로프로세서를 중심으로 발전해 왔다. 하지만 RISC 기반의 ARM, MIPS등의 범용 프로세서들은 점차 그 필요성이 커지고 있는 네트워크 기능과 멀티미디어 처리 기능 등에 대해서는 많은 고려 없이 설계된 프로세서들이다. 소규모 사업자 및 개인 사용자를 위한 네트워크 기기의 경우는 가격대비 성능이 우수한 제품이 시장을 차지하는데 유리하므로, 지금까지 대부분의 경우에서 전용 하드웨어를 사용하지 않고, PHY와 MAC layer 일부의 기본적인 기능을 제외한 나머지 네트워크 기능을 모두 상기한 내장 마이크로프로세서로 처리하고 있다. VDSL, FTTH과 같이 고속 인터넷을 가능하게 하는 기술이 발전함에 따라, 기존의 범용 프로세서에 기반을 둔 네트워크 기기는 빠른 속도로 그 성능의 한계에 다다르고 있다. 이는 단순히 프로세서의 동작 속도를 높이는 것으로 해결할 수 있는 문제가 아닌 것으로 보이며, 네트워크 프로토콜의 처리에 최적화 되어 있지 않은 범용 프로세서의 사용에 근본적인 문제점이 있다고 하겠다. 본 연구를 통하여 네트워크 기능 수행에 효율적인 네트워크 프로세서를 설계하고 이를 Home gateway용 SOC에 내장하고 성능을 측정하여 그 상용화 가능성을 타진한다.

플립칩 본더용 가열기의 열특성 해석을 위한 수치모델 (A Numerical Model to Analyze Thermal Behavior of a Radiative Heater Disigned for Flip-Chip Bonders)

  • 이상현;곽호상;한창수;류도현
    • 한국전산유체공학회지
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    • 제8권4호
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    • pp.41-49
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    • 2003
  • This study presents a numerical model to analyze dynamic thermal behavior of a hot chuck designed for flip-chip bonders. The hot chuck of concern is a heater which has been specifically developed for accomplishing high-speed and ultra-precision soldering. The characteristic features are radiative heat source and the heating tool made of a material of high thermal diffusivity. A physical modeling has been conducted for the network of heat transport. A simplified finite volume model is deviced to simulate time-dependent thermal behavior of the heating tool on which soldering is achieved. The reliability of the proposed numerical model is verified experimentally. A series of numerical tests illustrate the usefulness of the numerical model in design analysis.

적응생존형 네트워크 프로세서의 생존성 향상을 위한 유전알고리즘의 이용 (Genetic Algorithm for Improving the survivability of Self-Adaptive Network Processor)

  • 원주호;윤홍일
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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    • pp.703-706
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    • 2004
  • 공정기술의 발달과 컴퓨터 구조적인 발전에 의해서, 시스템의 동작속도가 기하급수적으로 증가하고 있다. 동작속도의 증가는 CMOS로 구현된 chip의 RC 특성에 의해서 timing variation 문제가 발생할 가능성이 높아지면서 테스트 비용이 전체 설계비용에서 차지하게 되는 비중이 급격하게 증가하고 있다. 따라서 온라인 테스트와 진화하드웨어 등이 테스트 비용감소를 위해서 연구되고 있다. 본 논문에서는 네트워크프로세서의 생존성을 위해서, 패킷엔진의 pipline의 각 stage사이의 clock slack borrowing을 이용해서 timing variation 문제를 자체적으로 해결할 수 있다는 것을 mixed-mode simulation을 통해서 통합 검증하였다. 또한 기존의 off-chip 진화하드웨어에 비해서 on-chip구현을 통해서 진화하드웨어의 성능향상과 메모리에 의해서 발생하는 overhead를 감소시키는 것이 가능함을 확인했다.

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MLP분류법을 적용한 가스분류기능의 칩 설계 및 응용 (Chip design and application of gas classification function using MLP classification method)

  • 장으뜸;서용수;정완영
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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    • pp.309-312
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    • 2001
  • A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

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EIA-709.1 Control Network Protocol을 이용한 필드버스 시스템 구현 (Implementation of a Fieldbus System Based on EIA-709.1 Control Network Protocol)

  • 최병욱;김정섭;이창희;김종배;임계영
    • 제어로봇시스템학회논문지
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    • 제6권7호
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    • pp.594-601
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    • 2000
  • EIA-709.1 Control Network Protocol is the basic protocol of LonWorks systems that is emerg-ing as a fieldbus device. In this paper the protocol is implemented by using VHDL with FPGA and C program on an Intel 8051 processor. The protocol from the physical layer to the network layer of EIA-709.1 is im-plemented in a hardware level,. So it decreases the load of the CPU for implementing the protocol. We verify the commercial feasibility of the hardware through the communication test with Neuron Chip. based on EIA-709.1 protocol which is used in industrial fields. The developed protocol based on FPGA becomes one of IP can be applicable to various industrial field because it is implemented by VHDL.

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LonRF 지능형 디바이스 기반의 유비쿼터스 홈네트워크 테스트베드 개발 (Development of a LonRF Intelligent Device-based Ubiquitous Home Network Testbed)

  • 이병복;박애순;김대식;노광현
    • 제어로봇시스템학회논문지
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    • 제10권6호
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    • pp.566-573
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    • 2004
  • This paper describes the ubiquitous home network (uHome-net) testbed and LonRF intelligent devices based on LonWorks technology. These devices consist of Neuron Chip, RF transceiver, sensor, and other peripheral components. Using LonRF devices, a home control network can be simplified and most devices can be operated on LonWorks control network. Also, Indoor Positioning System (IPS) that can serve various location based services was implemented in uHome-net. Smart Badge of IPS, that is a special LonRF device, can measure the 3D location of objects in the indoor environment. In the uHome-net testbed, remote control service, cooking help service, wireless remote metering service, baby monitoring service and security & fire prevention service were realized. This research shows the vision of the ubiquitous home network that will be emerged in the near future.

유무선 통신용 MEMS 온습도 네트워크 센서 (MEM Temperature and Humidity Network Sensor for Wire and Wireless Network)

  • 정우철;차부상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.360-361
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    • 2006
  • This paper describes a wire and wireless network sensor for temperature and humidity measurements. The network sensor comprises PLC(Power Line Communication) and RF transmitter(433MHz) for acquiring an internal (on-board) sensor signal, and measured data is transmitted to a main processing unit. The network sensor module is consist of MEMS sensor, 10-bit A/D converter, pre-amp., gain-amp., ADUC812 one chip processor and PLC/RF transmitting unit. The temperature and humidity sensor is based on MEMS piezoelectric membrane structure and is implemented by using dual function sensor for smart home and smart building.

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Inferring genetic regulatory networks of the inflammatory bowel disease in human peripheral blood mononuclear cells

  • Kim, Jin-Ki;Lee, Do-Heon;Yi, Gwan-Su
    • Bioinformatics and Biosystems
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    • 제2권2호
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    • pp.71-74
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    • 2007
  • Cell phenotypes are determined by groups of functionally related genes. Microarray profiling of gene expression provides us response of cellular state to its perturbation. Several methods for uncovering a cellular network show reliable network reconstruction. In this study, we present reconstruction of genetic regulatory network of inflammation bowel disease in human peripheral blood mononuclear cell. The microarray based on Affymetrix Gene Chip Human Genome U133 Array Set HG-U133A is processed and applied network reconstruction algorithm, ARACNe. As a result, we will show that inferred network composed of 450 nodes and 2017 edges is roughly scale-free network and hierarchical organization. The major hub, CCNL2 (cyclin A2), in inferred network is shown to be associated with inflammatory function as well as apoptotic function.

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디지털 신경회로망의 하드웨어 구현을 위한 재구성형 모듈러 디자인의 적용 (A reconfigurable modular approach for digital neural network)

  • 윤석배;김영주;동성수;이종호
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 하계학술대회 논문집 D
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    • pp.2755-2757
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    • 2002
  • In this paper, we propose a now architecture for hardware implementation of digital neural network. By adopting flexible ladder-style bus and internal connection network into traditional SIMD-type digital neural network architecture, the proposed architecture enables fast processing that is based on parallelism, while does not abandon the flexibility and extensibility of the traditional approach. In the proposed architecture, users can change the network topology by setting configuration registers. Such reconfigurability on hardware allows enough usability like software simulation. We implement the proposed design on real FPGA, and configure the chip to multi-layer perceptron with back propagation for alphabet recognition problem. Performance comparison with its software counterpart shows its value in the aspect of performance and flexibility.

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