• International Journal of Computer Science & Network Security
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• v.24 no.1
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• pp.107-118
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• 2024

With the seamless growth of the technology, network usage requirements are expanding day by day. The majority of electronic devices are capable of communication, which strongly requires a secure and reliable network. Network-based intrusion detection systems (NIDS) is a new method for preventing and alerting computers and networks from attacks. Machine Learning is an emerging field that provides a variety of ways to implement effective network intrusion detection systems (NIDS). Bagging and Boosting are two ensemble ML techniques, renowned for better performance in the learning and classification process. In this paper, the study provides a detailed literature review of the past work done and proposed a novel ensemble approach to develop a NIDS system based on the voting method using bagging and boosting ensemble techniques. The test results demonstrate that the ensemble of bagging and boosting through voting exhibits the highest classification accuracy of 99.98% and a minimum false positive rate (FPR) on both datasets. Although the model building time is average which can be a tradeoff by processor speed.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.67-75
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• 1997

This paper presents a virtual-parallel multistage interconnection network (MIN) which provides multipath between processor and memory module. The proposed virtual-parallel MIN network which uses $m{\times}1$ mutiplexer at the input switching block, $1{\times}m$ demultiplexer at the output switching block and logN-1 switching stages has maximum $2{\times}m$ unique paths between processor and memory module. Because it has multi-redundance paths, a number of processors can connect a specific Also, this new virtual-parallel structured MIN network can reduce packet collision possibility at switching block and it has cost. It shown to improve a performance and to be a very simple structure in comparision with MBSF structured MIN.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.1
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• pp.50-57
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• 2004

Two processors are generally used to drive the power circuits for controlling the dual motors independently. In this paper, we propose the new control scheme to drive dual inverters using only one controller with the aid of CAN network. The proposed system is very useful compared to conventional techniques especially in case of controlling the combined dual motors because the control algorithm can be implemented by the software program only without any additional processor or hardware interfacing. The proposed system is implemented and verified experimentally.

• Journal of Information Processing Systems
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• v.14 no.1
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• pp.270-279
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• 2018

PCI Express (PCIe) bus, which was only used as an internal I/O bus of a computer system, has expanded its function to outside of a system, with progress of PCIe switching processor. In particular, advanced features of PCIe switching processor enable PCIe bus to serve as an interconnection network as well as connecting external devices. As PCIe switching processors more advanced, it is required to consider the different adapter card architecture. This study developed multipurpose adapter cards by applying an on-board optical module, a latest optical communications element, in order to improve transfer distance and utilization. The performance evaluation confirmed that the new adapter cards with long cable can provide the same bandwidth as that of the existing adapter cards with short copper cable.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.53-62
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• 2010

Recently, various industrial embedded systems including vehicles controlled electronically are evolving to distributed multi-micro controller system. Accordingly, there is a need for standard CAN(Controller Area Network) protocol that ensures high stability and reliability of communication and is simple to construct object-oriented system with high control efficiency. CAN communication interface used general-purpose processor doesn't have many limitations in various application development because of fixed hardware architecture. This paper design and implement a CAN communication interface system based on FPGA. It is verified function and performance of system through monitoring communication with existing AT90CAN128 controller. Implemented CAN communication interface can be reused in development of application systems based on FPGA. And it provides low-cost, small-size and low-power design advantages.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.48-58
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• 2006

This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.283-290
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• 2006

The cellular neural networks have the structure that consists of an array of the same cell which is a simple processing element, and each of the cells has local connectivity and space invariant template properties. So, it has a very suitable structure for the hardware implementation. But, it is impossible to have a one-to-one mapping between the CNN hardware processors and the pixels of the practical large image. In this paper, a $5{\times}5$ CNN hardware processor with pipeline input and output that can be applied to the time-multiplexing processing scheme, which processes the large image with a small CNN cell block, is designed. the operation of the implemented $5{\times}5$ CNN hardware processor is verified from the edge detection and the shadow detection experimentations.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.8
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• pp.361-371
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• 2008

In this paper, the hypercube, hyperpetersen networks, whose degree is increasing in accordance with expansion of number of node and complete binary tree are one-to-one embedded into peterson-torus(PT) network which has fixed degree. The one-to-one embedding has less risk of overload or idle for the processor comparative to one-to-many and many-to-one embedding. For the algorithms which were developed on hypercube or hyperpetersen are used for PT network, it is one-to one embedded at expansion ${\doteqdot}1$, dilation 1.5n+2 and link congestion O(n) not to generate large numbers of idle processor. The complete binary tree is embedded into PT network with link congestion =1, expansion ${\doteqdot}5$ and dilation O(n) to avoid the bottleneck at the wormhole routing system which is not affected by the path length.

• Journal of Digital Contents Society
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• v.3 no.1
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• pp.89-99
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• 2002

Saturation routing algorithm is known to be an effective routing mechanism for tactical application and packet radio networks, since it minimizes the call set-up time and does not have to maintain routing tables. But, it is known that it has significant drawbacks with respect to the network efficiency, the overhead on the control messages [1]. We consider a tactical circuit-switched grid network with a maximum of tour links and two priority classes of voice traffic. Using the minimum first-derivative length (MFDL) path, we improve the blocking probability performance of a circuit-switched network without increasing the call set-up time and processor loading of the algorithm.