• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.9-12
• /
• 1999

The 6Bone is an environment supporting experimentation with the IPv6 protocols and products implementing it. Several functions of IPv6 remain loosely defined or undefined but the protocols related on IPv6 are being developed continuously. It is clear that ATM(Asynchronous Transfer Mode) technology is playing a important role in the evolution of the Internet as a transmission medium. In this paper, we suggest a design plan for the 6Bone overlayed on the existing ATM network, KOREN(Korea Research and Education Network). The planed 6Bone will become a good testbed to develop new networking technology and new services related on IPv6.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1991.10a
• /
• pp.150-154
• /
• 1991

As subsriber's requirements for high quality of telecom service are increased, a telecommunication network becomes complex and huge, and its management becomes an essential and an important factor in the evolution of telecommunication networks. In this paper, we focus on the network performance management and discuss the strategy of near real-time performance evaluation and control in Korea Telecome (KT) networks.

• Electronics and Telecommunications Trends
• /
• v.33 no.2
• /
• pp.22-29
• /
• 2018

A multi-channel network(MCN) is an organization that works with video platforms, such as YouTube, to offer assistance to channel owners in areas such as "products, programming, funding, cross-promotion, partner management, digital rights management, monetization/sales, and/or audience development" in exchange for a percentage of the ad revenue from the channel. This paper examines the market trends, business trends, and future evolution of an MCN. It also examines the status of the MCN industry in the media industry and the strategic direction for future industry development.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.18 no.8
• /
• pp.1939-1951
• /
• 1994

This study introduces a new tool breakage detecting technology comprised of an unsupervised neural network combined with adaptive time series autoregressive(AR) model where parameters are estimated recursively at each sampling instant using a parameter adaptation algorithm based on an RLS(Recursive Least Square). Experiment indicates that AR parameters are good features for tool breakage, therefore it can be detected by tracking the evolution of the AR parameters during milling process. an ART 2(Adaptive Resonance Theory 2) neural network is used for clustering of tool states using these parameters and the network is capable of self organizing without supervised learning. This system operates successfully under the wide range of cutting conditions without a priori knowledge of the process, with fast monitoring time.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2001.12a
• /
• pp.255-258
• /
• 2001

This paper is implementation of cellular automata neural network system which is a living creatures' brain using evolving hardware concept. Cellular automata neural network system is based on the development and the evolution, in other words, it is modeled on the ontogeny and phylogeny of natural living things. The proposed system developes each cell's state in neural network by CA. And it regards code of CA rule as individual of genetic algorithm, and evolved by genetic algorithm. In this paper we implement this system using evolving hardware concept Evolving hardware is reconfigurable hardware whose configuration is under the control of an evolutionary algorithm. We design genetic algorithm process for evolutionary algorithm and cells in cellular automata neural network for the construction of reconfigurable system. The effectiveness of the proposed system is verified by applying it to time-series prediction.

• ETRI Journal
• /
• v.38 no.3
• /
• pp.463-468
• /
• 2016

With the constant increase in network traffic, wireless operators are finding it more challenging to keep network hardware costs to a minimum. At the same time, the energy cost associated with operating a network has increased proportionally. Therefore, the search for higher network capacity is simultaneously accompanied by the search for a cost-efficient network deployment. In this paper, we show that a saving in transmitted signal energy can be achieved at the signal design level by deploying very specific signal processing techniques. Using an orthogonal frequency-division multiplexing signal for Long-Term Evolution networks as an example, we utilize a novel non-uniform companding quantizer to save a transmitted signal energy. Our results show that by using non-uniform quantization it is possible to further optimize 4G wireless networks.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.18 no.7
• /
• pp.1881-1897
• /
• 1994

This paper presents a neural network-based computational scheme to generate the optimized robotic assembly sequence for an assembly product consisting of a number of parts. An assembly sequence is considered to be optimal when it meets a number of conditions : it must satisfy assembly constraints, keep the stability of in-process subassemblies, and minimize assembly cost. To derive such an optimal sequence, we propose a scheme using both the Hopfield neural network and the expert system. Based upon the inferred precedence constraints and the assembly costs from the expert system, we derive the evolution equation of the network. To illustrate the suitability of the proposed scheme, a case study is presented for industrial product of an electrical relay. The result is compared with that obtained from the expert system.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.9
• /
• pp.71-79
• /
• 1993

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.

• Proceedings of the KIEE Conference
• /
• 1998.07c
• /
• pp.961-963
• /
• 1998

Power telecommunication networks, being used to support the operation and management of power utility services, exhibits different characteristics from those of public domain networks. KEPCO is planning to evolve its own power network infrastructure to exploit ATM (Asynchronous Transfer Mode) technology. The ATM network to be developed needs to effectively utilize existing network of KEPCO and to fully support new and emerging power-utility-services. This paper summarizes the features of power communication services and the characteristics of Power telecommunication networks, and reports our evolution methodology for KEPCO network.

• Fire Science and Engineering
• /
• v.10 no.2
• /
• pp.28-39
• /
• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.