• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1345-1352
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• 2014

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.48-55
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• 2017

This paper proposes a new link structure that transmits power, clock, and data through a single optical fiber for a future automotive network. A pulse-position modulation (PPM) technique is adopted to guarantee a DC-balanced signal for robust power transmission regardless of transmitted data pattern. Further, circuit implementations and theoretical analyses for the proposed PPM transceiver are described in this paper. A prototype transceiver fabricated in 65-nm CMOS technology, is used to verify the PPM signaling part of the proposed system. The prototype achieves a $10^{-13}$ bit-error rate and 0.188-UI high frequency jitter tolerance while consuming 14 mW at 800 Mb/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12A
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• pp.1120-1135
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• 2005

In this paper, We have design and implement the network synchronization module for NG-SDH system having 120 Gbps capacity. and also evaluate the performance of it. We also propose analyzing algorithm clock characterisrics on NG-SDH node clock based on the evaluation results.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.677-680
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• 2003

In this paper, the analysis of practical end-to-end delay in worst case is performed for distributed control system considering the implementation of the system. The control system delay is composed of the delay caused by multi-task scheduling of operating system, the delay caused by network communication, and the delay caused by the asynchronous between them. Through simulation tests based on CAN(Controller Area Network), the proposed end-to-end delay in worst case is validated. Additionally, online clock synchronization algorithm is proposed here for the control system. Through another simulation test, the online algorithm is proved to have better performance than offline one in the view of network bandwidth utilization.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2113-2120
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• 2009

User authentication has been one of the most important part of the network system. OTP(One-Time Password) has been developed and applied to the existing authentication system. OTP makes a different password and abrogates used password each time when user is authenticated by the server. Those systems prevent stolen-key-problems which is caused by using the same key every log-in trial. Yet, OTP still has vulnerabilities. In this paper, an advanced protocol which is using clock-count method to apply a stream cipher algorithm to OTP protocols and to solve problems of existing OTP protocols is proposed.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.275-280
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• 2009

Femtocells are viewed as a promising option for mobile operators to improve coverage and provide high-data-rate services in a cost-effective manner Femtocells can be used to serve indoor users, resulting in a powerful solution for ubiquitous indoor and outdoor coverage. TThe frequency accuracy and phase alignment is necessary for ensuring the quality of service (QoS) forapplications such as voice, real-time video, wireless hand-off, and data over a converged access medium at the femtocell. But, the GPS has some problem to be used at the femtocell, because it is difficult to set-up, depends on the satellite condition, and very expensive. The IEEE 1588 specification provides a low-cost means for clock synchronisation over a broadband Internet connection. The Time of Packet (ToP) specified in IEEE 1588 is able to synchronize distributed clocks with an accuracy of less than one microsecond in packet networks. However, the timing synchronization over packet switched networks is a difficult task because packet networks introduce large and highly variable packet delays. This paper proposes an enhanced filter algorithm to reduce ths packet delay variation effects and maintain ToP slave clock synchronization performance. The results are presented to demonstrate in the intra-networks and show the improved performance case when the efficient ToP filter algorithm is applied.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.417-426
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• 1996

The end-to-end service clock recovery is a critical issue in providing constandt bit rate service through ATM network. The Synchronous Residual Time Stamp(SRTS) algorithm is used to recovery the source clock using time stamp of transmitter. In thispaper, we propose a Differential Residual Time Stamp (DRTS) transmission mechanism to effectively deliver the timing information of source clock in SRTS algorithm. The RTS transmission method simple in its hardware. From the results of field trial of DS3 rate interactive video communication system through B-ISDN testbed, it can be identified that DRTS method is superior to the RTS method.

• The KIPS Transactions:PartA
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• v.19A no.4
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• pp.181-186
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• 2012

The distributed measurement and control system require technology to solve complex synchronization problem among distributed devices. It can be solved by using IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems to synchronize real-time clocks incorporated within each component of the system. In this paper, we implemented the IEEE 1588v2 PTP emulator on BlueScope BL6000A using a delay request-response mechanism to measure clock synchronization.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.11
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• pp.1144-1149
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• 2009

This paper deals with the time synchronization problem over SpaceWire links. SpaceWire is a standard for high-speed links and networks between spacecraft components, which was invented for better, cheaper, faster on-board data handling in spacecraft. The standard defines Time-Code for time distribution over SpaceWire network. When a Time-Code is transmitted, transmission delay and jitter is unavoidable. In this paper, a mechanism to remove Time-Code transmission delay and jitter over SpaceWire links is proposed and implemented with FPGA for validation. The proposed mechanism achieves high resolution clock synchronization over SpaceWire links, complies with the standard and can be easily adopted over SpaceWire network.