• Journal of Positioning, Navigation, and Timing
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• v.13 no.3
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• pp.221-235
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• 2024

Errors included in Global Navigation Satellite System (GNSS) measurements degrade the performance of user position estimation but can be mitigated by spatial correlation properties. Augmentation systems providing correction data can be broadly categorized into State Space Representation (SSR) and Observation Space Representation (OSR) methods. The satellite-based cm-level augmentation service based on the SSR broadcasts correction data via satellite signals, unlike the traditional Real-Time Kinematic (RTK) and Network RTK methods, which use OSR. To provide a large amount of correction data via the limited bandwidth of the satellite communication, efficient message structure design considering service area, correction generation, and broadcast intervals is necessary. For systematic message design, it is necessary to analyze the influence of error components included in GNSS measurements. In this study, errors in satellite orbits, satellite clocks for GPS, Galileo, BeiDou, and QZSS satellite constellations ionospheric and tropospheric delays over one year were analyzed, and their spatial decorrelations and linear modeling characteristics were examined.

• Journal of Broadcast Engineering
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• v.19 no.4
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• pp.439-452
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• 2014

This paper suggests the method to extend service area by using the transmit offset delay in T-DMB single frequency network (SFN). In general, synchronization of the transmit time of all site can be done by using the reference clock of GPS, which dose not reflect the details geographical characteristics and transmit specifications of each site. Applying the site-specific transmit offset delay, we could extend the service area of SFN T-DMB. Applying the transmit offset delay, it is found that the signal quality in the region of weak receive field strength was improved and upto 4~8 km service area expansion was achieved by satisfying the minimum field strength ($45dB{\mu}V/m$) recommended by the Korea Communications Commission (KCC). Site-specific offset delay was calculated considering the geographic service area characteristics, distribution of electric field strength between neighboring sites and site-specific service target area. Experiments were carried out in order to analyze impact of calculated offset delay on the T-DMB SFN and also to confirm that the offset delay extends T-DMB service coverage. The experiment was done in metropolitan T-DMB service areas.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.896-905
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• 2010

The sensor networks can be used attractively for various application areas. Time synchronization is important for any Ubiquitous Sensor Networks (USN) systems. USN makes extensive use of synchronized time in many contexts for data fusion. However existing time synchronization protocols are available only for homogeneous sensor nodes of USN. It needs to be extended or redesigned in order to apply to the USN with heterogeneous sensor nodes. Because heterogeneous sensor nodes have different clock sources with the SinkNode of USN, it is impossible to be synchronized global time. In addition, energy efficiency is one of the most significant factors to influence the design of sensor networks, as sensor nodes are limited in power, computational capacity, and memory. In this paper, we propose specific time synchronization based on master-slave topology for the global time synchronization of USN with heterogeneous sensor nodes. The time synchronization master nodes are always able to be synchronized with the SinkNode. Then time synchronization master nodes enable time synchronization slave nodes to be synchronized sleep periods. The proposed master-slave time synchronization for heterogeneous sensor nodes of USN is also helpful for power saving by maintaining maximum sleep time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.100-110
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• 2001

In this paper, we investigated several buffer management schemes for the design of shared-memory type ATM switches, which can enhance the utilization of switch resources and can support quality-of-service (QoS) functionalities. Our results show that dynamic threshold (DT) scheme demonstrate a moderate degree of robustness close to pushout(PO) scheme, which is known to be impractical in the perspective of hardware implementation, under various traffic conditions such as traffic loads, burstyness of incoming traffic, and load non-uniformity across output ports. Next, we considered buffer management strategies to support QoS functions, which utilize parameter values obtained via connection admission control (CAC) procedures to set tile threshold values. Through simulations, we showed that the buffer management schemes adopted behave well in the sense that they can protect regulated traffic from unregulated cell traffic in allocating buffer space. In particular, it was observed that dynamic partitioning is superior in terms of QoS support than virtual partitioning.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.235-240
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• 2006

The paper will give an overview of the mission of GalTeC and then concentrate on two main aspects. The first more detailed aspect, is the analysis of the key performance parameters for the Galileo system services and presenting a technical overview of methods and algorithms used. The second more detailed aspect, is the service volume prediction including service dimensioning using the Prediction tool. In order to monitor and validate the Galileo SIS performance for Open Service (OS) and Safety Of Life services (SOL) regarding the key performance parameters, different analyses in the SIS domain and User domain are considered. In the SIS domain, the validation of Signal-in-Space Accuracy SISA and Signal-in-Space Monitoring Accuracy SISMA is performed. For this purpose first of all an independent OD&TS and Integrity determination and processing software is developed to generate the key reference performance parameters named as SISRE (Signal In Space Reference Errors) and related over-bounding statistical information SISRA (Signal In Space Reference Accuracy) based on raw measurements from independent sites (e.g. IGS), Galileo Ground Sensor Stations (GSS) or an own regional monitoring network. Secondly, the differences of orbits and satellite clock corrections between Galileo broadcast ephemeris and the precise reference ephemeris generated by GalTeC will also be compared to check the SIS accuracy. Thirdly, in the user domain, SIS based navigation solution PVT on reference sites using Galileo broadcast ephemeris and the precise ephemeris generated by GalTeC are also used to check key performance parameters. In order to demonstrate the GalTeC performance and the methods mentioned above, the paper presents an initial test result using GPS raw data and GPS broadcast ephemeris. In the tests, some Galileo typical performance parameters are used for GPS system. For example, the maximum URA for one day for one GPS satellite from GPS broadcast ephemeris is used as substitution of SISA to check GPS ephemeris accuracy. Using GalTeC OD&TS and GPS raw data from IGS reference sites, a 10 cm-level of precise orbit determination can be reached. Based on these precise GPS orbits from GalTeC, monitoring and validation of GPS performance can be achieved with a high confidence level. It can be concluded that one of the GalTeC missions is to provide the capability to assess Galileo and general GNSS performance and prediction methods based on a regional and global monitoring networks. Some capability, of which first results are shown in the paper, will be demonstrated further during the planned Galileo IOV phase, the Full Galileo constellation phase and for the different services particularly the Open Services and the Safety Of Life services based on the Galileo Integrity concept.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.