• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
• /
• pp.109-109
• /
• 2000

Recently, carbon nanotube has been investigating for field emission display ( (FED) applications due to its high electron emission at relatively low electric field. However, the growing of carbon nanotube generally requires relatively high temperature processing such as arc-discharge (5,000 ~ $20,000^{\circ}C$) and laser evaporation (4,000 ~ $5,000^{\circ}C$) methods. In this presentation, low temperature growing of carbon nanotube by plasma enhanced chemical vapor deposition (PECVD) using nickel catalyst which is compatible to conventional FED processing temperature will be described. Carbon n notubes with average length of 100 run and diameter of 2 ~ $3\mu$ill were successfully grown on silicon substrate with native oxide layer at $550^{\circ}C$using nickel catalyst. The morphology and microstructure of carbon nanotube was highly depended on the processing temperature and nickel layer thickness. No significant carbon nanotube growing was observed with samples deposited on silicon substrates without native oxide layer. This is believed due to the formation of nickel-silicide and this deteriorated the catalytic role of nickel. The formation of nickel-silicide was confirmed by x-ray analysis. The role of native oxide layer and processing parameter dependence on microstructure of low temperature grown carbon nanotube, characterized by SEM, TEM XRD and R없nan spectroscopy, will be presented.

• 전기학회논문지
• /
• 제59권1호
• /
• pp.130-133
• /
• 2010

Although many structures based on $SnO_2$ nanowires have been demonstrated, there is a limitation towards practical application due to the unwanted contact potential between the metal electrode and the $SnO_2$ nanowire. This is mostly due to the presence of the native oxide layer that acts as an insulator between the metal contact and the nanowire. In this study the contact properties between Ti/Au contacts and a single $SnO_2$ nanowire was compared to the electrical properties of a contact without the oxide layer. RIE(Reactive Ion Etching) is used to selectively remove the oxide layer from the contact area. The $SnO_2$ nanowires were synthesized by chemical vapor deposition (CVD) and dispersed on a $Si/Si_3N_4$ substrate. The Ti/Au (20nm/100nm) electrodes were formed bye-beam lithography, e-beam evaporation and a lift-off process.

• 한국수소및신에너지학회논문집
• /
• 제29권6호
• /
• pp.627-634
• /
• 2018

Gallium-based liquid metal, e.g., eutectic gallium-indium (EGaIn), is highly attractive as an electrode material for flexible and stretchable devices. On the liquid metal, oxide layer is spontaneously formed, which has a wide band-gap, and therefore is electrically insulating. In this paper, we fabricate a capacitor based on eutectic gallium-indium (EGaIn) liquid metal and investigate its cyclic voltammetry (CV) behavior. The EGaIn capacitor is composed of two EGaIn electrodes and electrolyte. CV curves reveal that the EGaIn capacitor shows the behavior of electric double-layer capacitors (EDLC), where the oxide layers on the EGaIn electrodes serves as the dielectric layer of EDLC. The oxide thicker than the spontaneously-formed native oxide decreases the capacitance of the EGaIn capacitor, due to increased voltage loss across the oxide layer. The EGaIn capacitor without oxide layer exhibits unstable CV curves during the repeated cycles, where self-repair characteristic of the oxide was observed. Finally, the electrolyte concentration is optimized by comparing the CV curves at various electrolyte concentrations.

• E2M - 전기 전자와 첨단 소재
• /
• 제8권3호
• /
• pp.352-356
• /
• 1995

Native oxide layer on MCT (HgCdTe) has been grown uniformly in H$\_$2/O$\_$2/ electrolyte through anodic oxidation method. It has been determined that anodic oxidation of HgCdTe in H$\_$2/O$\_$2/ electrolyte proceeds immediately with the input of constant currents without any induction time required for anodic oxideation in KOH electrolyte. Oxide layer with the resistivity of 2*10$\^$10/.ohm.cm and the refractive index of 2.1 suggested the possibility of well matching combination layer with ZnS for MCT MIS device. XPS results indicated that the major components of oxide layer grown in H202 solution is TeO$\_$2/ with the possibility of small amounts of CdTeO$\_$3/.

• 한국전기전자재료학회논문지
• /
• 제13권2호
• /
• pp.125-130
• /
• 2000

Two step growth of reduced pressure chemical vapor eposition has been successfully developed to achieve in-situ phosphorus-doped silicon epilayers, and the characteristic evolution on their microstructures has been investigated using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectroscopy. The two step growth, which employs heavily in-situ P doped silicon buffer layer grown at low temperature, proposes crucial advantages in manipulating crystal structures of in-situ phosphorus doped silicon. In particular, our experimental results showed that with annealing of the heavily P doped silicon buffer layers, high-quality epitaxial silicon layers grew on it. the heavily doped phosphorus in buffer layers introduces into native oxide and plays an important role in promoting the dispersion of native oxides. Furthermore, the phosphorus doping concentration remains uniform depth distribution in high quality single crystalline Si films obtained by the two step growth.

• 한국생산제조학회지
• /
• 제22권3_1spc호
• /
• pp.544-550
• /
• 2013

A grooved surface with anisotropic wettability was fabricated on a silicon substrate using photolithography, reactive ion etching, and a KOH etching process. The contact angles (CAs) of water droplets were measured and compared with the theoretical values in the Cassie state and Wenzel state. The experimental results showed that the contact area between a water droplet and a solid surface was important to determine the wettability of the water. The specimens with native oxide layers presented CAs ranging from $71.6^{\circ}$ to $86.4^{\circ}$. The droplets on the specimens with a native oxide layer could be in the Cassie state because they had relatively smooth surfaces. However, the CAs of the specimens with thick oxide layers ranged from $33.4^{\circ}$ to $59.1^{\circ}$. This indicated that the surface roughness for a specimen with a relatively thick oxide layer was higher, and the water droplet was in the Wenzel state. From the CA measurement results, it was observed that the wetting on the grooved surface was anisotropic for all of the specimens.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
• /
• pp.140.1-140.1
• /
• 2013

The native silicon-oxide (SiOx) layer at the metal/Silicon interface acts as an electrical resistance to the metal contact of devices. Various methods are proposed for removing this layer, such as sputtering before metal contact formation or high temperature annealing. We studied the chemical evolution of the Au/SiOx/Si system during the annealing at $500^{\circ}C$ using a spatially resolved photoelectron emission method. Scanning photoelectron emission microscopy (SPEM) and core level spectra from local area of the sample show the inhomogeneous oxidation and formation of silicide of Au, as well as valence band spectra reveals the role of Au atoms during the dissociation process of SiOx.

• 전자공학회논문지A
• /
• 제28A권5호
• /
• pp.380-386
• /
• 1991

Hydrogen plasma-assisted epitaxial(PAE) growth of GaAs/Si and GaAs/Ge/Si with Ge buffer layer has been investigated. By means of photoluminescence, Nomarski microscopu, and $\alpha$-step, it could be known that GaAs on Si with Ge buffer layer has better crystalline quality than GaAs on Si without Ge buffer layer. The stoichiometry of GaAs layer on Si was confirmed by the depth profile of Auger electron spectroscope (AES). Also the native oxide(SiO$_2$) layer on Si substrate was plama-etched and the removal of the oxide layer was confirmed by AES. Photoluminescence peak wavelength of GaAs/Ge/Si with Ge buffer of 1\ulcorner thickness and GaAs growth rate of 160$\AA$/min was 8700$\AA$and FWHM was 12$\AA$.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
• /
• pp.143.1-143.1
• /
• 2016

Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.

• 전기화학회지
• /
• 제20권1호
• /
• pp.1-6
• /
• 2017

본 연구에서는 구리 배선 공정에서 구리 씨앗층 표면에 형성되는 구리 자연산화물을 제거하는 표면 전처리가 후속 구리 전착에 미치는 영향을 살펴보았다. 구리 배선 공정의 화학적 기계적 연마 공정에서 사용하는 citric acid 기반의 용액을 구리 표면 전처리 과정에 적용하여 표면에 존재하는 구리 자연 산화물을 제거하였고, 용액 조성 변화를 통해 산화물 제거의 선택성을 높여 구리 씨앗층의 손실을 최소화하였다. 또한 표면 전처리 후 구리 전해 전착과 무전해 전착을 시도하여 전착한 박막의 비저항, 표면 거칠기 등의 성질을 비교하고, 이를 통해 선택적으로 구리 산화물을 제거한 이후에 전착된 박막의 비저항과 표면 거칠기가 가장 낮게 나타남을 확인하였다.