• Journal of Magnetics
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• v.10 no.2
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• pp.66-70
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• 2005

The junction properties between the ferromagnet (FM) and two-dimensional electron gas (2DEG) system are crucial to develop spin electronic devices. Two types of 2DEG layer, InAs and GaAs channel heterostructures, are fabricated to compare the junction properties of the two systems. InAs-based 2DEG layer with low trans-mission barrier contacts FM and shows ohmic behavior. GaAs-based 2DEG layer with $Al_2O_3$ tunneling layer is also prepared. During heat treatment at the furnace, arsenic gas was evaporated and top AlAs layer was converted to aluminum oxide layer. This new method of forming spin injection barrier on 2DEG system is very efficient to obtain tunneling behavior. In the potentiometric measurement, spin-orbit coupling of 2DEG layer is observed in the interface between FM and InAs channel 2DEG layers, which proves the efficient junction property of spin injection barrier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.115-120
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• 2008

Carrier velocity in the MOSFET channel is the main driving force for improved transistor performance with scaling. We report measurements of the drift velocity of electrons and holes in silicon inversion layers. A technique for extracting effective carrier velocity which is a more accurate extraction method based on the actual inversion charge measurement is used. This method gives more accurate result over the whole range of $V_{ds}$, because it does not assume a linear approximation to obtain the inversion charge and it does not limit the range of applicable $V_{ds}$. For a very short channel length device, the electron velocity overshoot is observed at room temperature in 37 nm MOSFETs while no hole velocity overshoot is observed down to 36 nm. The electron velocity of short channel device was found to be strongly dependent on the longitudinal field.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1034-1037
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• 2004

In this paper we fabricated a test panel for AMOLED on glass and PET substrate. The test panel consisted of the various size of OTFTs and OLEDs and the current driving capability of OTFTs for OLEDs has been investigated. OTFTs were made of the inverted staggered structure and employed polyvinylphenol (PVP) as the gate insulator and pentacene thin film as the active layer. The OTFTs produced the filed effect mobility of 0.3$cm^2$/V.sec and on/off current ratio of $10^5$. OLEDs consisted of TPD for HTL and Alq3 for EML with 35nm thick, generating green monochrome light. We found that OTFT with channel length of 70${\mu}m$and channel width of over 3.5mm provided the sufficient current to OLED to generate the luminescence of 0.3Cd/$m^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.1-8
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• 2006

In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that $N_{it}$ generation at the interface of $Si/SiO_2$ has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.630-640
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• 2007

As the range of sensor network's applicability is getting wider, it creates new application areas which is required real-time operation, such as military and detection of radioactivity. However, existing researches are focused on effective management for resources, existing sensor network operating system cannot support to real-time areas. In this paper, we propose the ${\mu}TMO$ model which is lightweight real-time distributed object model TMO. We design the real-time sensor network operation system ${\mu}TMO-NanoQ+$ which is based on ETRI's sensor network operation system Nano-Q+. We modify the Nano-Q+'s timer module to support high resolution and apply Context Switch Threshold, Power Aware scheduling techniques to realize lightweight scheduler which is based on EDF. We also implement channel based communication way ITC-Channel and periodic thread management module WTMT.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1118-1121
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• 2009

We have fabricated inverted staggered pentacene Thin Film Transistor (TFT) with 1-${\mu}m$ channel length by micro contact printing (${\mu}$-CP) method. Patterning of micro-scale source/drain electrodes without etching was successfully achieved using silver nano particle ink, Polydimethylsiloxane (PDMS) stamp and FC-150 flip chip aligner-bonder. Sheet resistance of the printed Ag nano particle films were effectively reduced by two step annealing at $180^{\circ}C$.

• Journal of Powder Materials
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• v.15 no.1
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• pp.31-36
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• 2008

In this study, the bottom-up powder metallurgy and the top-down severe plastic deformation (SPD) techniques for manufacturing bulk nanomaterials were combined in order to achieve both full density and grain refinement without grain growth of rapidly solidified Al-20 wt% Si alloy powders during consolidation processing. Continuous equal channel multi-angular processing (C-ECMAP) was proposed to improve low productivity of conventional ECAP, one of the most promising method in SPD. As a powder consolidation method, C-ECMAP was employed. A wide range of experimental studies were carried out for characterizing mechanical properties and microstructures of the ECMAP processed materials. It was found that effective properties of high strength and full density maintaining nanoscale microstructure are achieved. The proposed SPD processing of powder materials can be a good method to achieve fully density and nanostructured materials.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.109-114
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• 2002

In this paper, we have presented the simulation results ah)ut threshold voltage for Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n channel MOSFETs with gate lengths from 180 to 30 nm in accordance to the constant voltage scaling theory and the lateral scaling. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region is due to scaling down. We investigated and analyzed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.804-810
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• 2005

An analytical subthreshold swing (SS) model has been presented for double gate MOSFET(DGMOSFET) in this study. The results calculated by this model are more precise for about 10nm channel length and thickness than those derived from the previous models. The results of this model are compared with Medici simulation to varify the validity of this model, and good agreementes have been obtained. The changes of SS have been investigated for various channel lengths, channel thicknesses and gate oxide thicknesses using this model, given that these parameters are very important in design of DGMOSFET. This demonstrates that the proposed model provides useful data for design of nano-scale DGMOSFET. It is Known that the SS is improved to smaller ratios of channel thickness vs channel length and is smaller in very thin oxides. New gate dielectric materials with high permittivity have to be developed to enable design of nano-scale DGMOSFET.