• 한국진공학회:학술대회논문집
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• 한국진공학회 1998년도 제14회 학술발표회 논문개요집
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• pp.68-69
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• 1998

Nano-crystalline silicon(nc-Si) thin films were directly depposited by ion beam assisted electron beam depposition (IBAED) method. The visibe luminescence in IBAED sampples were originated from not an oxygen bond but Si nano-crystallites. And we can conclude that the ion beam would be contribute to the suppression of the Si-O bond formation.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.1035-1038
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• 2002

The electrical properties of Porous polycrystalline silicon Nano-Structure (PNS) as a cold cathode were investigated as a function of anodizing condition, the thickness of Au film as a top electrode and the substrate temperature. Non-doped 2${\mu}m$-polycrystalline silicon was electrochemically anodized in HF: ethanol (=1:1) mixture as a function of the anodizing condition including a current density and anodizing time. After anodizing, the PNS was thermally oxidized for 1 hr at 900 $^{\circ}C$. Then, 20nm, 30nm, 45nm thickness of Au films as a top electrode were deposited by E-beam evaporator. Among the PNSs fabricated under the various kinds of anodizing conditions, the PNS anodized at a current density of 10mA/$cm^2$ for 20 sec has the lowest turn-on voltage and the highest emission current than those of others. Also, the electron emission properties were investigated as functions of measuring temperature and the different thickness of Au film as a top-electrode.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.414-415
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• 2007

PMMA light guiding plate with nano pattern was fabricated by nano imprinting technology. Silicon mold was fabricated by conventional photolithography. A nickel stamper was fabricated by electroplating process using silicon mold. Nano imprinting was performed on PMMA plate at $140^{\circ}C$ under pressure of 20kN. The nano pattern on PMMA plate was investigated using FE-SEM.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.727-730
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• 2003

Thin tin oxide film with nano-size particle was prepared on silicon substrate by hydrothermal synthetic method and successive sol-gel spin coating method. The fabrication method of tin oxide film with ultrafine nano-size crystalline structure was tried to be applied to fabrication of micro gas sensor array on silicon substrate. The tin oxide film on silicon substrate was well patterned by chemical etching upto 5${\mu}{\textrm}{m}$width and showed very uniform flatness. The tin oxide film preparation method and patterning method were successfully applied to newly proposed 2-dimensional micro sensor fabrication.

• 한국항공우주학회지
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• 제31권2호
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• pp.57-62
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• 2003

MEMS(미소전기기계시스템) 박막의 푸와송비 측정을 위한 미소굽힙기법이 제안되었다. 푸와송비 측정에 민감한 쌍원시편(두 개의 원모양)을 설계하고 표면미세가공 공정을 사용하여 제작하였다. 미소압입기로 하중을 가한 쌍원시편의 하중-변위 곡선을 분석하여 푸와송비를 측정할 수 있었다. 제안도니 미소굽힘기법은 표면미세가공에 적합하여 소자제작과정에서의 동시측정이 가능하고(in-situ measurement), 소자가 위치해 있는 작은 영영에서의 물성을 국부적으로 측정할 수 있는 장점이 있다. 제안된 기법을 검증하기 위하여 저압화학기상증착법에 의하여 증착된 2.3㎛ 다결정실리콘(Poly-silicon)의 푸와송비를 측정하였다. 실험에 사용된 다결정실리콘막의 푸와송비는 0.2569 이고 쌍원시편의 강성에 대한 측정표준편차는 2.66% 이었다.

• 마이크로전자및패키징학회지
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• 제13권3호
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• pp.13-17
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• 2006

밀도가 높고 주기적인 배열의 기공과 나노패턴이 된 텅스텐 나노점이 실리콘 산화물/실리콘 기판위에 형성이 되었다. 기공의 지름은 25 nm이고 깊이는 40 nm 이었으며 기공과 기공 사이의 거리는 60 nm이었다. nm 크기의 패턴을 형성시키기 위해서 자기조립물질을 사용했으며 폴리스티렌(PS) 바탕에 벌집형태로 평행하게 배열된 실린더 모양의 폴리메틸메타아크릴레이트(PMMA)의 구조를 형성했다. 폴리메틸메타아크릴레이트를 아세트산으로 제거하여 폴리스티렌만 남아있는 건식 식각용 마스크를 만들었다. 실리콘 산화막은 불소 기반의 화학반응성 식각법을 이용하여 식각했다. nm크기의 트렌치 안에 선택적으로 증착된 텅스텐 나노점을 만들기 위해서 저압화학기상증착(LPCVD)방법을 이용하였다. 텅스텐 나노점과 실리콘 트렌치의 지름은 26 nm 와 30 nm였다.

• KIEE International Transactions on Electrophysics and Applications
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• 제2C권5호
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• pp.258-261
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• 2002

Electrical forming dependent current-voltage (I-V) and numerically derived differential conductance(dI／dV) characteristics have been presented in the multi-layer nano-crystalline silicon／oxygen (no-Si／O) superlattice. Distinct staircase-like features, indicating the presence of resonant tunnel barriers, are clearly observed in the dc I-V characteristics. Also, all samples showed a continuous change in current and zero conductivity around OV corresponding to the Coulomb blockade in the calculated dI／dV-V curve. Also, Ra-man scattering measurement showed the presence of a nano-crystalline Si structure. This result becomes a step in the right direction for the fabrication of silicon-based optoelectronic and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in high speed and low power silicon MOSFET devices of the future.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1266-1269
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• 2007

Polycrystalline silicon (poly-Si) films were prepared directly on plastic substrates at a low (< $200^{\circ}C$) by using Catalytic Chemical Vapor Deposition (Cat-CVD) technique without subsequent annealing steps. Surface roughness of the poly-Si layer and the density of the gate dielectric layer were found to be influential to the TFT performance.

• 대한금속재료학회지
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• 제49권9호
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• pp.732-738
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• 2011

Silicon oxide thin films were deposited by using a plasma-enhanced chemical-vapor deposition technique to investigate the light emission properties. The photoluminescence characteristics were divided into two categories along the relative ratio of the flow rates of $SiH_4$ and $N_2O$ source gases, which show light emission in the broad/visible range and a light emission peak at 380 nm. We attribute the broad/visible light emission and the light emission peak to the quantum confinement effect of nanocrystalline silicon and the Si=O defects, respectively. Changes in the photoluminescence spectra were observed after the post-annealing processes. The photoluminescence spectra of the broad light emission in the visible range shifted to the long wavelength and were saturated above an annealing temperature of $900^{\circ}C$ or after 1 hour annealing at $970^{\circ}C$. However, the position of the light emission peak at 380 nm did not change at all after the post-annealing processes. The light emission intensities at 380 nm initially increased, and decreased at annealing temperatures above $700^{\circ}C$ or after 1 hour annealing at $700^{\circ}C$. The photoluminescence behaviors after the annealing processes can be explained bythe size change of the nanocrystalline silicon and the density change of Si=O defect in the films, respectively. These results support the possibility of using a silicon-based light source for Si-optoelectronic integrated circuits and/or display devices.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.37.1-37.1
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• 2011

Miniaturization of lenses has been widely researched by various scientific and engineering techniques. As a result, micro scaled lens structure could be easily achieved from various fabrication techniques; nevertheless it is still challenging to make nano scaled lenses. This paper reports a novel fabrication method of silicon nanotemplate for nanolens array. The inverse structure of nanolens array was fabricated on silicon substrate by reactive ion etching (RIE) process. This technique has a flexibility to produce different tip shapes using different pattern masks. Once the silicon nano-tip array structure is well-defined using an optimized recipe, it is followed by polymer molding to duplicate nanolens array from the template. Finally, the nanostructures formed on silicon nanotemplate and polymer replica were investigated using FE-SEM and AFM measurements. The nano scaled lens can be manufactured from the same template, also using other replication techniques such as imprinting, injection molding and so on.