• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.52-52
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• 2011

A novel deposition process for n-type nanocrystalline silicon (n-type nc-Si) thin films at room temperature has been developed by adopting the neutral beam assisted chemical vapor deposition (NBa-CVD). During formation of n-type nc-Si thin film by the NBa-CVD process with silicon reflector electrode at room temperature, the energetic particles could induce enhance doping efficiency and crystalline phase in polymorphous-Si thin films without additional heating on substrate; The dark conductivity and substrate temperature of P-doped polymorphous~nano crystalline silicon thin films increased with increasing the reflector bias. The NB energy heating substrate(but lower than $80^{\circ}C$ and increase doping efficiency. This low temperature processed doped nano-crystalline can address key problem in applications from flexible display backplane thin film transistor to flexible solar cell.

• Korean Journal of Materials Research
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• v.33 no.6
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• pp.257-264
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• 2023

To develop a high capacity lithium secondary battery, a new approach to anode material synthesis is required, capable of producing an anode that exceeds the energy density limit of a carbon-based anode. This research synthesized carbon nano silicon composites as an anode material for a secondary battery using the RF thermal plasma method, which is an ecofriendly dry synthesis method. Prior to material synthesis, a silicon raw material was mixed at 10, 20, 30, 40, and 50 wt% based on the carbon raw material in a powder form, and the temperature change inside the reaction field depending on the applied plasma power was calculated. Information about the materials in the synthesized carbon nano silicon composites were confirmed through XRD analysis, showing carbon (86.7~52.6 %), silicon (7.2~36.2 %), and silicon carbide (6.1~11.2 %). Through FE-SEM analysis, it was confirmed that the silicon bonded to carbon was distributed at sizes of 100 nm or less. The bonding shape of the silicon nano particles bonded to carbon was observed through TEM analysis. The initial electrochemical charging/discharging test for the 40 wt% silicon mixture showed excellent electrical characteristics of 1,517 mAh/g (91.9 %) and an irreversible capacity of 133 mAh/g (8.1 %).

• Biotechnology and Bioprocess Engineering:BBE
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• v.8 no.4
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• pp.252-256
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• 2003

In this paper we describe the status of a silicon-based microelectrode for neural recording and an advanced neural interface. We have developed a silicon neural probe, using a combination of plasma and wet etching techniques. This process enables the probe thickness to be controlled precisely. To enhance the CMOS compatibility in the fabrication process, we investigated the feasibility of the site material of the doped polycrystalline silicon with small grains of around 50 nm in size. This silicon electrode demonstrated a favorable performance with respect to impedance spectra, surface topography and acute neural recording. These results showed that the silicon neural probe can be used as an advanced microelectrode for neurological applications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.699-704
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• 2018

One-dimensional nanostructures have attracted increasing attention because of their unique electronic, optical, optoelectrical, and electrochemical properties on account of their large surface-to-volume ratio and quantum confinement effect. Vertically grown nanowires have a large surface-to-volume ratio. The vapor-liquid-solid (VLS) process has attracted considerable attention for its self-alignment capability during the growth of nanostructures. In this study, vertically aligned silicon oxide nano-pillars were grown on Si\$SiO_2$(300 nm)\Pt substrates using two-zone thermal chemical vapor deposition system via the VLS process. The morphology and crystallographic properties of the grown silicon oxide nano-pillars were investigated by field emission scanning electron microscopy and transmission electron microscopy. The diameter and length of the grown silicon oxide nano-pillars were found to be dependent on the catalyst films. The body of the silicon oxide nano-pillars exhibited an amorphous phase, which is consisted with Si and O. The head of the silicon oxide nano-pillars was a crystalline phase, which is consisted with Si, O, Pt, and Ti. The vertical alignment of the silicon oxide nano-pillars was attributed to the preferred crystalline orientation of the catalyst Pt/Ti alloy. The vertically aligned silicon oxide nano-pillars are expected to be applied as a functional nano-material.

• Bulletin of the Korean Chemical Society
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• v.34 no.6
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• pp.1845-1847
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• 2013

The lateral photovoltaic effect (LPE) can be observed in semiconductors by irradiating a light spot position between electrodes on sample's surface. Because lateral photovoltaic voltage (LPV) is sensitively changed by light spot position, a LPE device has been tried as a position-sensitive detector. This study discusses the correlation between LPV and conductivity in p-type silicon and nano-structured Au deposited p-type silicon (nano-Au silicon), respectively. Conductivity measurement of the sample was carried out using the four-wire method to eliminate contact resistance, and conductivity dependence on LPV was simultaneously measured by changing the light irradiation position. The result showed a strong correlation between conductivity and LPV in the p-type silicon sample. The correlation coefficient was 0.87. The correlation coefficient between LPV and conductivity for the nano-Au silicon sample was 0.41.

• Proceedings of the Korean Vacuum Society Conference
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• 2007.02a
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• pp.117-117
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• 2007

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.175-177
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• 2002

Electrical characteristics of the Si-O superlattice diode as a function of annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy (MBE) system. Consequently, the experimental results of superlattice diode with multilayer Si-O structure showed the stable and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic and quantum device as well as for the replacement of silicon-on-insulator (SOI) in ultra high speed and lower power CMOS devices in the future, and it can be readily integrated with silicon ULSI processing.

• Korean Chemical Engineering Research
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• v.60 no.3
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• pp.446-451
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• 2022

In this study, to improve capacity and cycle stability, the pitch coated nano silicon sheets/CNT composites were prepared through electrostatic bonding of nano silicon sheets and CNT. Silica sheets were synthesized by hydrolyzing TEOS on the crystal planes of NaCl, and then nano silicon sheets were prepared by using magnesiothermic reduction method. To fabricate the nano silicon sheets/CNT composites, the negatively charged CNT after the acid treatment was used to assemble the positively charged nano silicon sheets modified with APTES. THF as a solvent was used in the coating process of PFO pitch. The physical properties of the prepared anode composites were analysed by FE-SEM, XRD and EDS. The electrochemical performances of the synthesized anode composites were performed by current charge/discharge, rate performances, differential capacity and EIS tests in the electrolyte LiPF₆ dissolve solvent (EC:DMC:EMC = 1:1:1 vol%). It was found that the anode material with high capacity and stability could be synthesized when high composition of silicon and conductivity of CNT were used. The pitch coated nano silicon sheets/CNT anode composites showed initial discharge capacity of 2344.9 mAh/g and the capacity retention ratio of 81% after 50 cycles. The electrochemical property of pitch coated anode material was more improved than that of the nano silicon sheets/CNT composites.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.48-52
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• 1998

We fabricated the newly proposed nano structure memory with SOI edge channel and a nano dot. The width of the edge channel of this device, which uses the side wall as a channel and has a nano dot on this channel region, was determined by the thickness of the recessed top-silicon layer of SOI wafer. The size of side-wall nano dot was determined by the RIE etch and E-Beam lithography. The I$_{d}$-V$_{d}$, I$_{d}$-V$_{g}$ characteristics of the devices without nano dots and memory characteristics of the devices with nano dots were obtained, where the voltage scan was done between -20 V and 14 V and the threshold voltage shift was about 1 V.t 1 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2004.08a
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• pp.163-163
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• 2004